Rainbow Electronics MAX5511 - Manual (Page 17)

An example of a custom fixed gain using the force-sense
output of the MAX5510/MAX5511 is shown in Figure 9. In
this example R1 and R2 set the gain for V
OUT .
V OUT = [(V REFIN x N A ) / 256] x [1 + (R2 / R1)]
where N A represents the numeric value of the DAC
input code.
Power Supply and Bypassing
Considerations
Bypass the power supply with a 0.1µF capacitor to GND.
Minimize lengths to reduce lead inductance. If noise
becomes an issue, use shielding and/or ferrite beads to
increase isolation. For the thin QFN package, connect
the exposed paddle to ground.
Layout Considerations
Digital and AC transient signals coupling to GND can
create noise at the output. Use proper grounding tech-
niques, such as a multilayer board with a low-inductance
ground plane. Wire-wrapped boards and sockets are not
recommended. For optimum system performance, use
printed circuit (PC) boards. Good PC board ground lay-
out minimizes crosstalk between DAC outputs, reference
inputs, and digital inputs. Reduce crosstalk by keeping
analog lines away from digital lines.
MAX5510/MAX5511
+1.8V to +5.5V, Ultra-Low-Power, 8-Bit,
Voltage-Output DACs
______________________________________________________________________________________ 17
Figure 9. Separate Force-Sense Outputs Create Unity and
Greater-than-Unity DAC Gains Using the Same Reference
REFIN
DAC
V OUT
OUT
MAX5510
FB
R2
R1
Figure 10. Software-Configurable Output Gain
H
L
FB W
N DAC IS THE NUMERIC VALUE OF THE DAC INPUT CODE.
N POT IS THE NUMERIC VALUE OF THE POT INPUT CODE.
REFIN
MAX5510
MAX5401
SOT-POT
100kΩ
DAC
VOUT
5PPM/°C
RATIOMETRIC
TEMPCO
1.8V ≤ V DD ≤ 5.5V
V OUT
V
OUT
=
V REFIN × N DAC
256
(
1 +
255 - N POT )
255
SCLK
DIN
CS2
CS1
Chip Information
TRANSISTOR COUNT: 10,688
PROCESS: BiCMOS