Rainbow Electronics MAX5889 - Manual (Page 5)

MAX5889
12-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
_______________________________________________________________________________________ 5
Note 2: This parameter does not include update-rate-dependent effects of sin(x)/x filtering inherent in the MAX5889.
Note 3: Parameter measured single-ended with 50
Ω double-terminated outputs.
Note 4: Not production tested. Guaranteed by design.
Note 5: Parameter defined as the change in midscale output caused by a
±5% variation in the nominal supply voltages.
ELECTRICAL CHARACTERISTICS (continued)
(AV DD3.3 = DV DD3.3 = AV CLK = +3.3V, AV DD1.8 = DV DD1.8 = +1.8V, external reference V REFIO = +1.2V, output load 50 Ω double-ter-
minated, transformer-coupled output, I OUT = 20mA, T A = -40°C to +85°C, unless otherwise noted. Specifications at T A
≥ +25°C are
guaranteed by production testing. Specifications at T A < +25°C are guaranteed by design and characterization. Typical values are at
T A = +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Minimum Common-Mode Voltage 1 V
Maximum Common-Mode
Voltage
1.9 V
Input Resistance R CLK Single-ended 5 k Ω
Input Capacitance C
CLK
3 pF
POWER SUPPLIES
AV DD3.3 3.135 3.3 3.465
Analog Supply Voltage Range
AV DD1.8 1.710 1.8 1.890
V
Clock Supply Voltage Range AV CLK 3.135 3.3 3.465 V
DV DD3.3 3.135 3.3 3.465
Digital Supply Voltage Range
DV DD1.8 1.710 1.8 1.890
V
f CLK = 100MHz, f OUT = 16MHz 26.5
f
CLK
= 500MHz, f
OUT
= 16MHz 26.5 28 I AVDD3.3
f CLK = 600MHz, f OUT = 16MHz 26.5
f CLK = 100MHz, f OUT = 16MHz 11.3
f CLK = 500MHz, f OUT = 16MHz 50 58
Analog Supply Current
I AVDD1.8
f CLK = 600MHz, f OUT = 16MHz 60
mA
f CLK = 100MHz, f OUT = 16MHz 2.8
f CLK = 500MHz, f OUT = 16MHz 2.8 3.6 Clock Supply Current I AVCLK
f CLK = 600MHz, f OUT = 16MHz 2.8
mA
f CLK = 100MHz, f OUT = 16MHz 0.2
f CLK = 500MHz, f OUT = 16MHz 0.2 0.5 I DVDD3.3
f CLK = 600MHz, f OUT = 16MHz 0.2
f CLK = 100MHz, f OUT = 16MHz 10.2
f CLK = 500MHz, f OUT = 16MHz 42 48
Digital Supply Current
I DVDD1.8
f CLK = 600MHz, f OUT = 16MHz 48
mA
f CLK = 100MHz, f OUT = 16MHz 137
f CLK = 500MHz, f OUT = 16MHz 263 297
f CLK = 600MHz, f OUT = 16MHz 292
mW
Total Power Dissipation P DISS
Power-down, clock static low,
data input static
13 µW
Power-Supply Rejection Ratio PSRR (Note 5) ±0.025 %FS