Rainbow Electronics MAX5081 - Manual (Page 13)

MAX5080/MAX5081
1A, 40V, MAXPower Step-Down
DC-DC Converters
______________________________________________________________________________________ 13
equal to 20% and 80%, respectively. ∆I
P-P is the peak-to-
peak inductor current (see the Input Capacitors Selection
section) and f
SW is the converter’s switching frequency.
The allowable deviation of the output voltage during
fast load transients also determines the output capaci-
tance, its ESR, and its equivalent series inductance
(ESL). The output capacitor supplies the load current
during a load step until the controller responds with a
greater duty cycle. The response time (t
RESPONSE
)
depends on the closed-loop bandwidth of the converter
(see the Compensation Design section). The resistive
drop across the output capacitors ESR, the drop
across the capacitors ESL (
∆V
ESL) , and the capacitor
discharge causes a voltage droop during the load-
step. Use a combination of low-ESR tantalum/aluminum
electrolyte and ceramic capacitors for better transient
load and voltage ripple performance. Nonleaded
capacitors and capacitors in parallel help reduce the
ESL. Keep the maximum output voltage deviation
below the tolerable limits of the electronics being pow-
ered. Use the following equations to calculate the
required ESR, ESL, and capacitance value during a
load step:
where I
STEP
is the load step, t
STEP
is the rise time of the
load step, and t
RESPONSE
is the response time of the
controller.
Compensation Design
The MAX5080/MAX5081 use a voltage-mode control
scheme that regulates the output voltage by comparing
the error amplifier output (COMP) with an internal ramp
to produce the required duty cycle. The output lowpass
LC filter creates a double pole at the resonant frequen-
cy, which has a gain drop of -40dB/decade. The error
amplifier must compensate for this gain drop and phase
shift to achieve a stable closed-loop system.
The basic regulator loop consists of a power modulator,
an output feedback divider, and a voltage error amplifi-
er. The power modulator has a DC gain set by
V
IN /V RAMP , with a double pole and a single zero set by
the output inductance (L), the output capacitance
(C OUT ) (C5 in the Typical Application Circuit) and its
equivalent series resistance (ESR). The power modula-
tor incorporates a voltage feed-forward feature, which
automatically adjusts for variations in the input voltage
resulting in a DC gain of 10. The following equations
define the power modulator:
The switching frequency is internally set at 250kHz or
can vary from 150kHz to 350kHz when driven with an
external SYNC signal. The crossover frequency (f
C
),
which is the frequency when the closed-loop gain is
equal to unity, should be set at 15kHz or below therefore:
f
C
≤15kHz
The error amplifier must provide a gain and phase
bump to compensate for the rapid gain and phase loss
from the LC double pole. This is accomplished by utiliz-
ing a type 3 compensator that introduces two zeroes
and 3 poles into the control loop. The error amplifier
has a low-frequency pole (f
P1 ) near the origin.
The two zeros are at:
and the higher frequency poles are at:
Compensation When f C < f ZESR
Figure 3 shows the error amplifier feedback as well as
its gain response for circuits that use low-ESR output
capacitors (ceramic). In this case f
ZESR
occurs after f
C
.
f Z1 is set to 0.8 x f LC(MOD) and f Z2 is set to f LC to com-
pensate for the gain and phase loss due to the double
pole. Choose the inductor (L) and output capacitor
(C
OUT
) as described in the Inductor and Output
Capacitor Selection section.
f
R C
and f
R
C C
C C
P P 2 3
1
2 6 6
1
2 5
7 8
7 8
=
Ч Ч
=
Ч Ч
Ч
+ ⎛
⎝⎜ ⎞
⎠⎟ π
π
f
1
f
1
Z1 Z2
=
Ч Ч
=
Ч + Ч 2 5 7 2 6 3 6 π π R C
and
R R C ( )
( )
G
V
V
f
L C
f
C ESR
MOD DC
IN
RAMP
LC
OUT
ZESR
OUT
= =
=
Ч
=
Ч Ч
10
1
2
1
2
π
π
E
V
C
V
E
V
ESR
STEP
OUT
STEP RESPONSE
Q
ESL STEP
STEP
SR
I
I t
SL
t
I
=
=
=
Ч
Ч
∆
∆
∆