Rainbow Electronics ADC12041 - Manual (Page 26)

Analog Application Information
(Continued)
INPUT CURRENT
At the start of the acquisition window (t AcqSYNOUT ) a charg-
ing current (due to capacitive switching) flows through the
analog input pins (ADCINa and ADCINb) The peak value
of this input current will depend on the amplitude and fre-
quency of the input voltage applied the source impedance
and the ADCINa and ADCINb input switch ON resistance
of 2500X
For low impedance voltage sources (1000 k X for 12 MHz
operation) the input charging current will decay to a value
that will not introduce any conversion errors before the end
of the default sample-and-hold (S H) acquisition time
(9 clock cycles) For higher source impedances (1000
l X
for 12 MHz operation) the S H acquisition time should be
increased to allow the charging current to settle within spec-
ified limits In asynchronous mode the acquisition time may
be increased to 15 47 or 79 clock cycles If different acqui-
sition times are needed the synchronous mode can be
used to fully control the acquisition time
INPUT BYPASS CAPACITANCE
External capacitors (0 01 mF – 0 1 mF) can be connected be-
tween the ADCINa and ADCINb analog input pins and the
analog ground to filter any noise caused by inductive pickup
associated with long leads
POWER SUPPLY CONSIDERATIONS
Decoupling and bypassing the power supply on a high reso-
lution ADC is an important design task Noise spikes on the
V
A
a (analog supply) or V
D
a (digital supply) can cause con-
version errors The analog comparator used in the ADC will
respond to power supply noise and will make erroneous
conversion decisions The ADC is especially sensitive to
power supply spikes that occur during the auto-zero or lin-
earity calibration cycles
The ADC12041 is designed to operate from a single a5V
power supply The separate supply and ground pins for the
analog and digital portions of the circuit allow separate ex-
ternal bypassing To minimize power supply noise and rip-
ple adequate bypass capacitors should be placed directly
between power supply pins and their associated grounds
Both supply pins should be connected to the same supply
source In systems with separate analog and digital sup-
plies the ADC should be powered from the analog supply
At least a 10 mF tantalum electrolytic capacitor in parallel
with a 0 1 mF monolithic ceramic capacitor is recommended
for bypassing each power supply The key consideration for
these capacitors is to have low series resistance and induc-
tance The capacitors should be placed as close as physi-
cally possible to the supply and ground pins with the smaller
capacitor closer to the device The capacitors also should
have the shortest possible leads in order to minimize series
lead inductance Surface mount chip capacitors are optimal
in this respect and should be used when possible
When the power supply regulator is not local on the board
adequate bypassing (a high value electrolytic capacitor)
should be placed at the power entry point The value of the
capacitor depends on the total supply current of the circuits
on the PC board All supply currents should be supplied by
the capacitor instead of being drawn from the external sup-
ply lines while the external supply charges the capacitor at
a steady rate
The ADC has two V
D
a and DGND pins It is recommended
to use a 0 1 mF plus a 10 mF capacitor between pin
21(V
D a ) and 22 (DGND) the SSOP and PLCC package
The layout diagram in Figure 10 shows the recommended
placement for the supply bypass capacitors
PC BOARD LAYOUT AND GROUNDING
CONSIDERATlONS
To get the best possible performance from the ADC12041
the printed circuit boards should have separate analog and
digital ground planes The reason for using two ground
planes is to prevent digital and analog ground currents from
sharing the same path until they reach a very low imped-
ance power supply point This will prevent noisy digital
switching currents from being injected into the analog
ground
Figure 10 illustrates a favorable layout for ground planes
power supply and reference input bypass capacitors It
shows a layout using a 28-pin PLCC socket and through-
hole assembly A similar approach should be used for the
SSOP package
The analog ground plane should encompass the area under
the analog pins and any other analog components such as
the reference circuit input amplifiers signal conditioning cir-
cuits and analog signal traces
The digital ground plane should encompass the area under
the digital circuits and the digital input output pins of the
ADC12041 Having a continuous digital ground plane under
the data and clock traces is very important This reduces
the overshoot undershoot and high frequency ringing on
these lines that can be capacitively coupled to analog cir-
cuitry sections through stray capacitances
The AGND and DGND in the ADC12041 are not internally
connected together They should be connected together on
the PC board right at the chip This will provide the shortest
return path for the signals being exchanged between the
internal analog and digital sections of the ADC
It is also a good design practice to have power plane layers
in the PC board This will improve the supply bypassing (an
effective distributed capacitance between power and
ground plane layers) and voltage drops on the supply lines
However power planes are not as essential as ground
planes are for satisfactory performance If power planes are
used they should be separated into two planes and the
area and connections should follow the same guidelines as
mentioned for the ground planes Each power plane should
be laid out over its associated ground planes avoiding any
overlap between power and ground planes of different
types When the power planes are not used it is recom-
mended to use separate supply traces for the V
A a and
V D a pins from a low impedance supply point (the regulator
output or the power entry point to the PC board) This will
help ensure that the noisy digital supply does not corrupt
the analog supply
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