Rainbow Electronics ADC12041 - Manual (Page 22)

Functional Description
The ADC12041 is programmed through a digital interface
that supports an 8-bit or 16-bit data bus The digital inter-
face consists of a 13-bit data input output bus (D
12 – D 0 )
digital control signals and two internal registers a write only
8-bit Configuration register and a read only 13-bit Data reg-
ister
The Configuration register programs the functionality of the
ADC12041 The 8 bits of the Configuration register are di-
vided into 5 fields Each field controls a specific function of
the ADC12041 the acquisition time synchronous or asyn-
chronous conversions mode of operation and the data bus
size
Features and Operating Modes
SELECTABLE BUS WIDTH
The ADC12041 can be programmed to interface with an
8-bit or 16-bit data bus The BW bit (b
3
) in the Configuration
register controls the bus size The bus width is set to 8 bits
(D
7 – D 0 are active and D 12 – D 8 are in TRI-STATE) if the BW
bit is cleared or 13 bits (D 12 – D 0 are active) if the BW bit is
set At power-up the default bus width is 8 bits (BW e 0)
In 8-bit mode the Configuration register is accessed with a
single write When reading the ADC in 8-bit mode the first
read cycle places the lower byte of the Data register on the
data bus followed by the upper byte during the next read
cycle
In 13-bit mode all bits of the Data register and Configuration
register are accessible with a single read or write cycle
Since the bus width of the ADC12041 defaults to 8 bits after
power-up the first action when 13-bit mode is desired must
be to set the bus width to 13 bits
WMODE
The WMODE pin is used to determine the active edge of the
write pulse The state of this pin determines which edge of
the WR signal will cause the ADC to latch in data This is
processor dependent If the processor has valid data on the
bus during the falling edge of the WR signal the WMODE
pin must be tied to V
D a This will cause the ADC to latch
the data on the falling edge of the WR signal If data is valid
on the rising edge of the WR signal the WMODE pin must
be tied to DGND causing the ADC to latch in the data on the
rising edge of the WR signal
ANALOG INPUTS
The ADCINa and ADCINb are the fully differential non-
inverting (positive) and inverting (negative) inputs into the
analog-to-digital converter (ADC) of the ADC12041
STANDBY MODE
The ADC12041 has a low power consumption mode (75 mW
5V) This mode is entered when a Standby command is
written in the command field of the Configuration register
The RDY ouput pin is high when the ADC12041 is in the
Standby mode Any command other than the Standby com-
mand written to the Configuration register will get the
ADC12041 out of the Standby mode The RDY pin will im-
mediately switch to a logic ‘‘0’’ when the ADC12041 is out
of the standby mode The ADC12041 defaults to the Stand-
by mode following a hardware power-up
SYNC ASYNC MODE
The ADC12041 may be programmed to operate in synchro-
nous (SYNC-IN) or asynchronous (SYNC-OUT) mode To
enter synchronous mode the SYNC bit in the Configuration
register must be set The ADC12041 is in synchronous
mode after a hardware power-up In this mode the SYNC
pin is programmed as an input and conversions are syn-
chronized to the rising edges of the signal applied at the
SYNC pin Acquisition time can also be controlled by the
SYNC signal when in synchronous mode Refer to the sync-
in timing diagrams When the SYNC bit is cleared the ADC
is in asynchronous mode and the SYNC pin is programmed
as an output In asynchronous mode the signal at the
SYNC pin indicates the status of the converter This pin is
high when the converter is performing a conversion Refer
to the sync-out timing diagrams
SELECTABLE ACQUISITION TIME
The ADC12041’s internal sample hold circuitry samples an
input voltage by connecting the input to an internal sampling
capacitor (approximately 70 pF) through an effective resist-
ance equal to the ‘‘On’’ resistance of the analog switch at
the input to the sample hold circuit (2500X typical) and the
effective output resistance of the source For conversion
results to be accurate the period during which the sampling
capacitor is connected to the source (the ‘‘acquisition time’’)
must be long enough to charge the capacitor to within a
small fraction of an LSB of the input voltage An acquisition
time of 750 ns is sufficient when the external source resist-
ance is less than 1 kX and any active or reactive source
circuitry settles to 12 bits in less than 500 ns When source
resistance or source settling time increase beyond these
limits the acquisition time must also be increased to pre-
serve precision
In asynchronous (SYNC-OUT) mode the acquisition time is
controlled by an internal counter The minimum acquisition
period is 9 clock cycles which corresponds to the nominal
value of 750 ns when the clock frequency is 12 MHz Bits b
0
and b 1 of the Configuration Register are used to select the
acquisition time from among four possible values (9 15 47
or 79 clock cycles) Since acquisition time in the asynchro-
nous mode is based on counting clock cycles it is also in-
versely proportional to clock frequency
T ACQ (ms) e
number of clock cycles
f CLK (MHz)
Note that the actual acquisition time will be longer than
T
ACQ
because acquisition begins either when the multiplex-
er channel is changed or when RDY goes low if the multi-
plexer channel is not changed After a read is performed
RDY goes high
which starts the T ACQ counter (see
Figure 7 )
In synchronous (SYNC-IN) mode bits b 0 and b 1 are ig-
nored and the acquisition time depends on the sync signal
applied to the SYNC pin The acquisition period begins on
the falling edge of RDY which occurs at the end of the
previous conversion (or at the end of an autozero or auto-
calibration procedure The acquisition period ends when
SYNC goes high
To estimate the acquisition time necessary for accurate
conversions when the source resistance is greater than
1 kX use the following expression
T ACQMIN (ms) e
0 75 (R S a R S H )
1 kX a R S H
e
0 75 (R S a 2500)
3500
where R
S
is the source resistance and R
S H
is the sample
hold ‘‘On’’ resistance
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