Rainbow Electronics MAX5104 User Manual

Page 8

MAX5104

Low-Power, Dual, Voltage-Output, 12-Bit DAC
with Serial Interface

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The MAX5104’s digital inputs are double buffered,
which allows any of the following: loading the input reg-
ister(s) without updating the DAC register(s), updating
the DAC register(s) from the input register(s), or updating
the input and DAC registers concurrently. The address
and control bits allow the DACs to act independently.
Send the 16-bit data as one 16-bit word (QSPI) or two
8-bit packets (SPI, MICROWIRE), with

CS low during

this period. The address and control bits determine
which register will be updated, and the state of the reg-
isters when exiting power-down. The 3-bit address/con-
trol determines the following:

• Registers to be updated
• Clock edge on which data is to be clocked out via the

serial-data output (DOUT)

• State of the user-programmable logic output

• Configuration of the device after power-down

The general timing diagram of Figure 5 illustrates how
data is acquired. Driving

CS low enables the device to

receive data; otherwise, the interface control circuitry is
disabled. With

CS low, data at DIN is clocked into the

CS goes high,

data is latched into the input and/or DAC registers,
depending on the address and control bits. The maximum
clock frequency guaranteed for proper operation is
10MHz. Figure 6 shows a more detailed timing diagram
of the serial interface.

DIN

SCLK

MOSI

SCK

I/O

SPI/QSPI

PORT

+5V

CPOL = 0, CPHA = 0

MAX5104

Figure 3. Connections for SPI/QSPI

Figure 5. Serial-Interface Timing Diagram

SCLK

DIN

COMMAND

EXECUTED

D11

D10

Figure 4. Serial-Data Format

1 Address/2 Control Bits

Address Bits

C1, C0

Control Bits

12 Data Bits

D11.......................D0

MSB...Data Bits...LSB

Sub

Bit

16 Bits of Serial Data

MSB...................................................................................LSB