Rainbow Electronics MAX19515 - Manual (Page 4)

MAX19515
Dual-Channel, 10-Bit, 65Msps ADC
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V AVDD = V OVDD = 1.8V, internal reference, differential clock, V CLK = 1.5V P-P , f CLK = 65MHz, A IN = -0.5dBFS, data output termination
= 50Ω, T A = -40°C to +85°C, unless otherwise noted. Typical values are at T A = +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
INTERCHANNEL CHARACTERISTICS
f INA or f INB = 70MHz at -1dBFS 95
Crosstalk
f INA or f INB = 175MHz at -1dBFS 85
dBc
Gain Match f IN = 70MHz ±0.05 dB
Offset Match f IN = 70MHz ±0.1 %FSR
Phase Match f IN = 70MHz ±0.5 D eg r ees
ANALOG OUTPUTS (CMA, CMB)
CMA, CMB Output Voltage V COM Default programmable setting 0.85 0.9 0.95 V
INTERNAL REFERENCE
REFIO Output Voltage V REFOUT 1.23 1.25 1.27 V
REFIO Temperature Coefficient TC REF < ±60 ppm/°C
EXTERNAL REFERENCE
REFIO Input-Voltage Range V REFIN
1.25 +5/
-10%
V
REFIO Input Resistance R REFIN
10
±20%
k Ω
CLOCK INPUTS (CLK+, CLK-)—DIFFERENTIAL MODE
Differential Clock Input Voltage 0.4 to 2.0 V
P-P
Self-biased 1.2 Differential Input Common-Mode
Voltage
DC-coupled clock signal 1.0 to 1.4
V
Differential, default 10 k Ω
Differential, internal termination selected 100 Ω Input Resistance R
CLK
Common mode 9 k Ω
Input Capacitance C CLK To ground, each input 3 pF
CLOCK INPUTS (CLK+, CLK-)—SINGLE-ENDED MODE (V CLK- < 0.1V)
Single-Ended Mode Selection
Threshold (V
CLK- )
0.1 V
Allowable Logic Swing (V CLK+ ) 0 - V AVDD V
Single-Ended Clock Input High
Threshold (V
CLK+
)
1.5 V
Single-Ended Clock Input Low
Threshold (V
CLK+ )
0.3 V
V CLK+ = V AVDD = 1.8V or 3.3V +0.5
Input Leakage (CLK+)
V CLK+ = 0 -0.5
µA
Input Leakage (CLK-) V CLK- = 0 -150 -50 µA
Input Capacitance (CLK+) 3 pF