Rainbow Electronics ADC10738 - Manual (Page 19)

Pin Descriptions
CLK The clock applied to this input controls the suc-
cessive approximation conversion time interval
the acquisition time and the rate at which the
serial data exchange occurs The rising edge
loads the information on the DI pin into the mul-
tiplexer address shift register This address con-
trols which channel of the analog input multi-
plexer (MUX) is selected The falling edge shifts
the data resulting from the A D conversion out
on DO CS enables or disables the above func-
tions The clock frequency applied to this input
can be between 5 kHz and 3 MHz
DI This is the serial data input pin The data applied
to this pln is shifted by CLK into the multiplexer
address register Tables I through III show the
multiplexer address assignment
DO The data output pin The A D conversion result
(DB0-SIGN) are clocked out by the failing edge
of CLK on this pin
CS This is the chip select input pin When a logic
low is applied to this pin the rising edge of CLK
shifts the data on DI into the address register
This low also brings DO out of TRI-STATE after
a conversion has been completed
PD This is the power down input pin When a logic
high is applied to this pin the A D is powered
down When a low is applied the A D is pow-
ered up
SARS This is the successive approximation register
status output pin When CS is high this pin is in
TRI-STATE With CS low this pin is active high
when a conversion is in progress and active low
at all other times
CH0 – CH7 These are the analog inputs of the MUX A
channel input is selected by the address infor-
mation at the DI pin which is loaded on the ris-
ing edge of CLK into the address register (see
Tables I – III)
The voltage applied to these inputs should not
exceed AV
a or go below GND by more than
50 mV Exceeding this range on an unselected
channel will corrupt the reading of a selected
channel
COM This pin is another analog input pln It can be
used as a ‘‘pseudo ground’’ when the analog
multiplexer is single-ended
V
REF
a This is the positive analog voltage reference in-
put In order to malntaln accuracy the voltage
range V
REF (V REF e V REF a – V REF b ) is
0 5 V DC to 5 0 V DC and the voltage at V REF a
cannot exceed AV a a 50 mV
V
REF b The negative voltage reference input In order to
maintain accuracy the voltage at this pin must
not go below GND b 50 mV or exceed AV
a
a 50 mV
AV a
DV a These are the analog and digital power supply
pins These pins should be tied to the same
power supply and bypassed separately The op-
erating voltage range of AV
a and DV a is
4 5 V
DC
to 5 5 V
DC
DGND This is the digital ground pin
AGND This is the analog ground pin
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