Quatech MPAP-100 - Manual (Page 32)

External/Status interrupt control WR15
Miscellaneous control bits: baud rate generator, DPLL control, auto
echo WR14
Lower byte of baud rate time constant WR13
Lower byte of baud rate time constant WR12
Clock mode and source control WR11
Miscellaneous transmitter/receiver control bits, NRZI, NRZ, FM
coding, CRC reset WR10
Master interrupt control and reset WR9
Transmit buffer WR8
Special HDLC Enhancement Register WR7'
Sync character (2nd byte) or SDLC Flag WR7
Sync character (1st byte) or SDLC address field WR6
Transmitter initialization and control WR5
Transmit/Receive miscellaneous parameters and codes, clock rate,
stop bits, parity WR4
Receiver initialization and control WR3
Interrupt vector WR2
Interrupt control, Wait/DMA request control WR1
Table 4 --- SCC write register description
For complete information regarding the SCC registers please refer to Zilog's Z85230
technical manual.