National Instruments NI 785xR - Manual (Page 16)

Chapter 1 Introduction
R Series Intelligent DAQ User Manual 1-6 ni.com
The FPGA does not retain the VI when the R Series device is powered off,
so you must reload the VI each time you power on the device. You can load
the VI from onboard flash memory or from software over the bus interface.
One advantage to using flash memory is that the VI can start executing
almost immediately after power up, instead of waiting for the computer to
completely boot and load the FPGA VI. Refer to the LabVIEW Help for
more information about how to store your VI in flash memory.
Reconfigurable I/O Applications
You can use the LabVIEW FPGA Module to create or acquire new VIs
for your application. The FPGA Module allows you to define custom
functionality for the R Series device using a subset of LabVIEW
functionality. Refer to the R Series examples, available in LabVIEW by
selecting Help»Find Examples, and then selecting Hardware Input and
Output»R Series, for examples of FPGA VIs.
Software Development
You can use LabVIEW with the LabVIEW FPGA Module to program the
NI 78xxR. To develop real-time applications that control the NI 78xxR, use
LabVIEW with the LabVIEW Real-Time Module.
LabVIEW FPGA Module
The LabVIEW FPGA Module enables you to use LabVIEW to create VIs
that run on the FPGA of the R Series target device. Use the FPGA Module
VIs and functions to control the I/O, timing, and logic of the R Series
device and to generate interrupts for synchronization. Select Help»Search
the LabVIEW Help to view the LabVIEW Help. In the LabVIEW Help,
use the Contents tab to browse to the FPGA Interface book for more
information about the FPGA Interface functions.
You can use Interactive Front Panel Communication to communicate
directly with the FPGA VI running on the FPGA target. You can use
Programmatic FPGA Interface Communication to programmatically
control and communicate with FPGA VIs from host VIs.
Use the FPGA Interface functions when you target LabVIEW for Windows
or an RT target to create host VIs that wait for interrupts and control the
FPGA by reading and writing the FPGA VI running on the R Series device.