Kane Industries C6713CPU - Manual (Page 46)

H ARDWARE R EFERENCE G UIDE
MICRO - LINE
®
C6713CPU
Date : 28 November 2005
Doc. no. : C6713CPU_HRG
Iss./Rev : 1.1
Page : 46
7.2 Changing the Board Configuration
This chapter shows the different hardware board configurations. The factory defaults are listed
below. Some configuration settings may be changed by the user and are described in the
subsequent paragraphs. For changing other settings, please contact ORSYS.
Function
default setting
DSP clock speed same as DSP speed grade
HPI / McASP1 HPI
micro-line ® pin D30 termination 4.7K Ω pull-up
I 2 C #0 / FPGA I/O FPGA I/O
CLKS1 / SCL1 termination 10K Ω pull-down
FPGA IO without FPGA loaded FPGA-internal pull-up
Table 17: Factory default configuration summary
7.2.1 Location of modifiable components
C9
R81
R65 R67
Figure 10: Location of configuration elements (top side)