Kane Industries C6713CPU - Manual (Page 25)

H ARDWARE R EFERENCE G UIDE
MICRO - LINE
®
C6713CPU
Date : 28 November 2005
Doc. no. : C6713CPU_HRG
Iss./Rev : 1.1
Page : 25
CPUSPEED:
This bit can be used by application software to determine the DSP speed version and to program
the DSP's PLL accordingly.
CPUSPEED CPU clock frequency
0 225 MHz
1 300 MHz
FLASH_A19:
This bit represents the highest address line of the flash memory. When FLASH_A19 is 0 the lower
1 MB of the flash memory is selected. When FLASH_A19 is 1, the upper 1 MB of the flash memory
is selected. Application software usually does not need to access this bit, but use the provided
functions for runtime flash memory access from the board library (see [20]).
3.10.2 FPGA Control Register (FCR)
The FPGA control register is used by the Flash File System and the board library to load the
FPGA. Application software does not need to access this register. The FPGA can be loaded at any
time and it is also possible to reload it during runtime with a different design.
7 6 5 4 3 0
PROG DONE CFG_EN RESERVED RESERVED
r, w, 0 r, 0 r, w, 0 r, 0
PROG:
This bit controls the PROG_B input line of the FPGA. This bit only has an effect if CFG_EN is set
to 1. Please refer to the FPGA development kit documentation for details. During reset, the
PROG_B signal of the FPGA is active, independent of the state of the PROG bit. This clears the
FPGA on reset.
PROG PROG pin
0 driven high (idle, has no effect on the FPGA)
1 driven low (FPGA is cleared)
DONE:
This bit allows to read back the status of the FPGA DONE output line. Please refer to the FPGA
development kit documentation for details.
DONE Encoding
0 the FPGA isn't configured yet.
1 the FPGA has been successfully configured
CFG_EN:
This bit switches the dedicated configuration signals of the FPGA to idle states so that no current
flows from the 3.3V PLD into the 2.5V configuration inputs of the FPGA. The user must set this bit
to 1 before starting the configuration of the FPGA and reset it to 0 after completion of the
configuration process. Please refer to the FPGA development kit documentation for details.
CFG_EN Encoding
0
FPGA configuration isn't possible.
1 FPGA configuration signals are driven.
3.10.3 LED Control Register (LED)
This register can be used by application software to control the two LED’s connected to the PLD.
There are different possible sources to switch on the green LED.