Samsung M391B5773DH0 - Manual (Page 25)

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datasheet
DDR3L SDRAM
Rev. 1.0
Unbuffered DIMM
15. Input/Output Capacitance
[ Table 16 ] Input/Output Capacitance
NOTE : This parameter is Component Input/Output Capacitance so that is different from Module level Capacitance.
1. Although the DM, TDQS and TDQS pins have different functions, the loading matches DQ and DQS
2. This parameter is not subject to production test. It is verified by design and characterization.
The capacitance is measured according to JEP147("PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER( VNA)") with
V
DD
, V
DDQ
, V
SS
, V
SSQ
applied and all other pins floating (except the pin under test, CKE, RESET and ODT as necessary). V
DD
=V
DDQ
=1.5V, V
BIAS
=V
DD
/2 and on-die
termination off.
3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here
4. Absolute value of CCK-CCK
5. Absolute value of CIO(DQS)-CIO(DQS)
6. CI applies to ODT, CS, CKE, A0-A15, BA0-BA2, RAS, CAS, WE.
7. CDI_CTRL applies to ODT, CS and CKE
8. CDI_CTRL=CI(CTRL)-0.5*(CI(CLK)+CI(CLK))
9. CDI_ADD_CMD applies to A0-A15, BA0-BA2, RAS, CAS and WE
10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK))
11. CDIO=CIO(DQ,DM) - 0.5*(CIO(DQS)+CIO(DQS))
12. Maximum external load capacitance on ZQ pin: 5pF
Parameter Symbol
DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600
Units NOTE
Min Max Min Max Min Max Min Max
1.35V
Input/output capacitance
(DQ, DM, DQS, DQS, TDQS, TDQS)
CIO 1.5 2.5 1.5 2.5 1.5 2.3 1.2 2.3 pF 1,2,3
Input capacitance
(CK and CK)
CCK 0.8 1.6 0.8 1.6 TBD TBD TBD TBD pF 2,3
Input capacitance delta
(CK and CK)
CDCK 0 0.15 0 0.15 TBD TBD TBD TBD pF 2,3,4
Input capacitance
(All other input-only pins)
CI 0.75 1.3 0.75 1.3 0.75 1.3 0.75 1.3 pF 2,3,6
Input/Output capacitance delta
(DQS and DQS)
CDDQS 0 0.2 0 0.2 TBD TBD TBD TBD pF 2,3,5
Input capacitance delta
(All control input-only pins)
CDI_CTRL -0.5 0.3 -0.5 0.3 TBD TBD TBD TBD pF 2,3,7,8
Input capacitance delta
(all ADD and CMD input-only pins)
CDI_ADD_CMD -0.5 0.5 -0.5 0.5 TBD TBD TBD TBD pF 2,3,9,10
Input/output capacitance delta
(DQ, DM, DQS, DQS, TDQS, TDQS)
CDIO -0.5 0.3 -0.5 0.3 TBD TBD TBD TBD pF 2,3,11
Input/output capacitance of ZQ pin CZQ - 3 - 3 TBD TBD TBD TBD pF 2, 3, 12
1.5V
Input/output capacitance
(DQ, DM, DQS, DQS, TDQS, TDQS)
CIO 1.5 3.0 1.5 2.7 1.5 2.5 1.4 2.3 pF 1,2,3
Input capacitance
(CK and CK)
CCK 0.8 1.6 0.8 1.6 0.8 1.4 0.8 1.4 pF 2,3
Input capacitance delta
(CK and CK)
CDCK 0 0.15 0 0.15 0 0.15 0 0.15 pF 2,3,4
Input capacitance
(All other input-only pins)
CI 0.75 1.5 0.75 1.5 0.75 1.3 0.75 1.3 pF 2,3,6
Input capacitance delta
(DQS and DQS)
CDDQS 0 0.2 0 0.2 0 0.15 0 0.15 pF 2,3,5
Input capacitance delta
(All control input-only pins)
CDI_CTRL -0.5 0.3 -0.5 0.3 -0.4 0.2 -0.4 0.2 pF 2,3,7,8
Input capacitance delta
(all ADD and CMD input-only pins)
CDI_ADD_CMD -0.5 0.5 -0.5 0.5 -0.4 0.4 -0.4 0.4 pF 2,3,9,10
Input/output capacitance delta
(DQ, DM, DQS, DQS, TDQS, TDQS)
CDIO -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 pF 2,3,11
Input/output capacitance of ZQ pin CZQ - 3 - 3 - 3 - 3 pF 2, 3, 12