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Wire serial interface hardware design – Sierra Wireless WISMO218 User Manual

Page 39

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WA_DEV_W218_PTS_002

Rev 005

Page 39 of 109

Product Technical Specification &

Customer Design Guidelines

5-wire serial interface hardware design:

Signal: CT103/TXD*, CT104/RXD*, ~CT105/RTS*, ~CT106/CTS*

The signal ~CT108/DTR* must be managed following the V24 protocol signaling if we want to

use idle mode.

For detailed configuration, please refer to Figure 10 Example of V24/CMOS Serial Link
Implementation for 5-wire UART.

4-wire serial interface hardware design:

Signal: CT103/TXD*, CT104/RXD*, ~CT105/RTS*, ~CT106/CTS*

The signal ~CT108/DTR* can be looped back to ~CT107/DSR from both the WISMO218 side

and from the DTE side.

For detailed configuration, please refer to Figure 9 Example of V24/CMOS Serial Link
Implementation for 4-wire UART.

2-wire serial interface hardware design:

This case is possible for a connected external chip, but it is not recommended.

The flow control mechanism has to be managed from the customer side.

Signal: CT103/TXD*, CT104/RXD*

The signal ~CT108/DTR* can be looped back to ~CT107/DSR from both the WISMO218 side

and from the DTE side.

The signals ~CT105/RTS*, ~CT106/CTS* are not used, please configure using the AT

command, AT + IFC = 0,0 (see document [2] WISMO218 AT Commands Manual).

The signal ~CT105/RTS* can be looped back to ~CT106/CTS* from both the WISMO218 side

and from the DTE side.

For detailed configuration, please refer to Figure 8 Example of V24/CMOS Serial Link
Implementation for 2-wire UART.

Note:

The loop back connection of ~CT108/DTR* to ~CT107/DSR is not allowed when the case
AT+PSSLEEP=0 is used, for which sleep mode entry is ~CT108/DTR* level dependent. (Refer to
Note 1 of the

Power Consumption

section. In order to go to sleep mode properly under such

configuration, AT+PSSLEEP=1 should be used instead. For details, please refer to document [2]
WISMO218

AT Commands Manual.

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According to PC (DTE) view