Juniper Networks M-Series - Manual (Page 6)

Page 6
M-series Routing Platforms
Forwarding and
Switch Interface
Boards M7i, M10i CFEB
Compact Forwarding Engine Board
• M7i router
• 8.4 Gbps throughput rate (4.2-Gbps full duplex)
• Optional Adaptive Services Module
• M10i router
• 12.8-Gbps throughput rate (6.4-Gbps full duplex)
• Does not support Adaptive Services Module
• 266-MHz CPU and supporting logic
• Internet Processor II-based ASIC for 16-Mpps packet lookup
• Two enhanced I/O Manager ASICs
• Parsing, prioritizing, and queuing of packets
• 4-MB parity-protected SSRAM per I/O Manager ASIC
• 8-MB SSRAM for forwarding tables associated with
ASICs
• 200 ms of delay-bandwidth buffering
• Two 512-KB boot flash EPROM (programmable on the board)
M20 SSB
System and Switch Board
• 25.6-Gbps throughput (12.8-Gbps full duplex)
• One Internet Processor II ASIC for 40-Mpps packet lookup
• Two Distributed Buffer Manager ASICs for coordinating pooled, single-stage buffering
• 33-MHz PCI bus, which connects the PowerPC 603e processor and the Internet
Processor II ASIC
• 512-KB boot flash EPROM (programmable on the board)
• Optional redundancy
• 16-MB Version
• PowerPC 603e processor running at 266 MHz for handling exception packets
• 16-MB SSRAM
• 256-MB DRAM
M40e SFM
Switching and Forwarding Module
• 51.2-Gbps throughput (25.6-Gbps full duplex)
• One Internet Processor II ASIC for 40-Mpps aggregate packet
lookup
• Two Distributed Buffer Manager ASICs for coordinating
pooled, single-stage buffering
• 256-KB parity-protected Level 2 cache
• Optional redundancy
• 16-MB Version
• PowerPC 603e processor running at 266 MHz
• 16-MB parity-protected SSRAM
• 256-MB parity-protected DRAM
M320 SIB
Switch Interface Board for interconnecting FPCs
• Four required per M320 chassis; all four active
• 80-Gbps throughput per SIB, 320 Gbps throughput per system
• Processor subsystem 300-MHz CPU
• System controller
• 256-MB DRAM
• Two Fast Ethernet interfaces
FPC M20
• 3.2-Gbps full-duplex throughput per FPC
• Enhanced I/O Manager ASIC
• Parsing, prioritizing, and queuing of packets
• 2-MB parity-protected SSRAM per I/O Manager ASIC
• 200 ms of delay-bandwidth buffering per FPC
M40e
• 3.2-Gbps full-duplex throughput per M40e-FPC, M40e-FPC1, and M40e-FPC2
• Two Packet Director ASICs for dispersing and balancing packets across the enhanced
I/O Manager ASICs
• Two enhanced I/O Manager ASICs
• Parsing, prioritizing, and queuing of packets
• 2-MB parity-protected SSRAM per I/O Manager ASIC
• 200 ms of delay-bandwidth buffering per FPC
M320
• 4-Gbps full-duplex throughput per M320-FPC1
• 16-Gbps full-duplex throughput per M320-FPC2
• 20-Gbps full-duplex throughput per M320-FPC3
• Layer 2 / Layer 3 Packet Processing ASICs
• Switch Interface ASICs
• Internet Processor ASICs
• Memory subsystem, including Queuing and Memory Interface
ASICs
• Processor subsystem