Intel 8086-1 - Manual (Page 18)

8086
WAVEFORMS (Continued)
MINIMUM MODE (Continued)
231455 – 14
SOFTWARE HALT
RD WR INTA
e V OH
DT R e INDETERMINATE
NOTES
1 All signals switch between V
OH
and V
OL
unless otherwise specified
2 RDY is sampled near the end of T 2 T 3 T W to determine if T W machines states are to be inserted
3 Two INTA cycles run back-to-back The 8086 LOCAL ADDR DATA BUS is floating during both INTA cycles Control
signals shown for second INTA cycle
4 Signals at 8284A are shown for reference only
5 All timing measurements are made at 1 5V unless otherwise noted
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