Motorola CP150TM - Manual (Page 30)

June, 2005 6880309N62-C
4-4 136-162 MHz VHF Theory Of Operation: VHF Frequency Generation Circuitry
4.3.4 Antenna Matching Network
The harmonic filter presents a 50
Ω impedance to antenna jack J140. A matching network, made up
of C140-C141 and L140, is used to match the antenna impedance to the harmonic filter. This
optimizes the performance of the transmitter and receiver into the impedance presented by the
antenna, significantly improving the antenna's efficiency.
4.3.5 Power Control
The power control circuit is a dc-coupled amplifier whose output is the dc gate bias voltage (VGG)
applied to the two stages of the RF power amplifier U110.
The output power of the transmitter is adjusted by varying the setting of the power-set DAC contained
in the ASFICcmp IC (DACG, U451 pin 6). This PWR_SET voltage is applied to U150 pin 3.
Stage U150-2 compares the voltage drop across current sense resistor R150 to the voltage drop
across resistor R151 caused by current flow through Q150, and adjusts its output (pin 7) to maintain
equal voltages at pins 5 and 6. Thus the current flow through Q150, and hence its emitter voltage, is
proportional to the current drawn by stage U110, which is in turn proportional to the transmitter output
power. The emitter voltage of Q150 is applied to U150 pin 2, where it is compared to the power set
voltage PWR_SET at pin 3.
The output of U150 pin 1 is divided by R110 and R111 and applied as a gate voltage to the power
amplifier U110. By varying this gate voltage as needed to keep the voltages at U150 pins 2 and 3
equal, power is maintained at the desired setting. Excessive final current, for example due to antenna
mismatch, causes a lowering of the voltage at U150 pin 6, an increased voltage at pin 2, and a
lowering of the voltage at pin 1 and of the gate voltage VGG. This prevents damage to the final stage
due to excessive current.
4.4 VHF Frequency Generation Circuitry
The frequency generation system, shown in Figure 4-3 , is composed of two circuit blocks, the
Fractional-N synthesizer IC U201, the VCO/Buffer IC U251, and associated circuitry. Figure 4-4
shows the peripheral interconnect and support circuitry used in the synthesizer block, and Figure 4-5
details the internal circuitry of the VCOBIC and its interconnections to the surrounding components.
Refer to the schematic to identify reference designators.
The Fractional-N synthesizer is powered by regulated 5 V and 3 V provided by U310 and U330
respectively. 5 V is applied to U201 pins 13 and 30, and 3 V is applied to pins 5, 20, 34 and 36. The
synthesizer in turn generates a super-filtered 4.5 V supply (VSF, from pin 28) to power U251. In
addition to the VCO, the synthesizer also interfaces with the logic and ASFICcmp circuits.
Programming for the synthesizer is accomplished through the microprocessor SPI_DATA_OUT,
SPI_CLK, and SYNTH_CS (chip select) lines (U409 pins 100, 1 and 47 respectively). A logic high
(3 V) from U201 pin 4 indicates to the microprocessor that the synthesizer is locked.