Sundance SMT300Q v.1.6 - Manual (Page 49)

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999
Mailbox Write/Read Interrupt Status Register(Offset: Write 0xD8, BAR0 Read 0xDA,
BAR0) – bit 0 of the write register (0xD8) must be cleared.**
Local Bus Interrupt Status Register(Offset 0x76, BAR0) – bit 7 must be cleared.
To cause the interrupt the DSP needs to write to the mailbox register in the V
3
chip,
this is done by writing to address 0x1C0000C0 (this will write to the first four
mailboxes).
*These are two separate registers, one to enable interrupts on reads from the
mailbox registers the other to enable interrupts on writes to the mailbox registers.
**These are two separate registers, one shows interrupt status for reads from the
mailbox register the other to show interrupt status on writes to the mailbox registers.