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6 – adc conversion time, Adc conversion time – Maxim Integrated DS4830 Optical Microcontroller User Manual

Page 49

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DS4830 User’s Guide

49

3. S/H0 has priority over S/H1 if both S/Hs are ready for conversion. However, in next slot for S/H, the S/H1 will get

slot even if S/H0 is also ready.

For example, if the ADC sequence mode conversion is enabled for channel 0, 4, 5, 6 and all secondary channels are
enabled and ready for conversion then the sequence of conversion is performed as shown in figure 7-3

CH0

Temp

Sample

1

CH4

S/H0

CH5

S/H1

CH6

S/H0

CH0

S/H1

CH4

……..

……..

One of the temperature

sensors & both S/H are ready

for conversion. Temperature

sensor gets priority as it

occurs after approx. 2ms.

Every alternate

channel is primary

channel

Both S/H0 & S/H1 are

ready. S/H0 gets

priority over S/H1

S/H1 gets chance

here even if S/H0

is ready.

Sequence

keeps

repeating

Temp

Sample

2

……..

SH0 or 1 if

triggered by

internal or

SHEN0/1l

Temperature Sample 1 and 2 conversions are ~2msec apart

Figure 7-3: ADC Frame Sequence

1.

Temperature channels can’t occur simultaneously in sequence as they share the same resources on chip.

2. Both Sample and Hold channels can occur simultaneously as they have dedicated resources.


7.1.6

– ADC Conversion Time

The ADC clock is derived from the system clock with divide ratio defined by the ADC Clock Divider Bits ADCCLK [2:0] in
the ADC Control register (ADCN). Each sample takes 15 ADC clock cycles to complete. Two of the 15 ADC clock cycles
are used for sample acquisition, and the remaining 13 clocks are used for data conversion. The ADC automatically reads
each measurement twice and outputs the average of the two readings. This makes the resulting time for one complete
conversion 30 ADC clock cycles. Additionally, 4 core clocks are used in data processing for each of the two readings.
Knowing this, it is possible to calculate the fastest ADC sample rate. The fastest ADC clock is:

ADC Clock = Core Clock / 8 = 10 MHz / 8 = 1250 kHz
One conversion requires 30 ADC Clocks + 8 Core Clocks

Conversion Time = (30 ADC Clocks Time+ 8 Core Clocks Time)

= 30 * 0.8 + 0.8

s

= 24.8

s per ADC Conversion

Sample Rate = 40.3 ksps


The ADC has an internal power management system that automatically shuts down the ADC when conversions are
complete by clearing ADCONV to 0. After being shut down, the ADC begins conversions again when the ADCONV bit is
set to 1 again. After ADCONV is set to 1, the ADC requires 20 ADCCLK cycles to setup and power up prior to beginning
the first conversion of the sequence. So the first ADC conversion time is ~40

s at the fastest ADC Clock. If the quick trip

is also enabled and if the ADC controller and the quick trip are sampling the same channel, the ADC sampling is delayed
by two quick trip conversions (3.2

s) to prevent collision.


In applications where extending the acquisition time is desired, the user can make use of the ADC Acquisition Extension
Bits (ADACQ[3:0] in the ADCN register). When the ADC Acquisition Extension is enabled (ADACQEN=1), the sample will
be acquired over a prolonged period during the sample acquisition. The extended acquisition time will be determined by