Socket Mobile Pentium 4 Full Size PICMG CPU Card IB810 - Manual (Page 42)

BIOS SETUP
38 IB810 User’s Manual
DRAM Data Integrity Mode
This BIOS setting is used to configure your RAM's data integrity mode.
ECC stands for Error Checking and Correction and it should only be used
if you are using 72-bit ECC RAM. This will enable the system to detect
and correct single-bit errors. It will also detect double-bit errors though it
will not correct them. This provides increased data integrity and system
stability at the expense of a little speed.
Memory Frequency For
This field sets the frequency of the DRAM memory installed. The default
setting is Auto. The other settings are PC200 and PC266.
DRAM Read Thermal Mgmt
This option enables or disables the DRAM Read thermal management
function.
System BIOS Cacheable
The setting of Enabled allows caching of the system BIOS ROM at
F000h-FFFFFh, resulting in better system performance. However, if any
program writes to this memory area, a system error may result.
Video BIOS Cacheable
The Setting Enabled allows caching of the video BIOS ROM at
C0000h-F7FFFh, resulting in better video performance. However, if any
program writes to this memory area, a system error may result.
Video RAM Cacheable
This feature enables or disables the caching of the video RAM at
A0000h-AFFFFh via the L2 cache.
Memory Hole At 15M-16M
In order to improve performance, certain space in memory can be reserved
for ISA cards. This memory must be mapped into the memory space
below 16 MB. The choices are Enabled and Disabled.
Delayed Transaction
The chipset has an embedded 32-bit posted write buffer to support delay
transactions cycles. Select Enabled to support compliance with PCI
specification version 2.1.