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7 mei state transactions, Table 3-7, Mei state transitions – IBM POWERPC 750GL User Manual

Page 147

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User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

gx_03.fm.(1.2)
March 27, 2006

Instruction-Cache and Data-Cache Operation

Page 147 of 377

3.7 MEI State Transactions

Table 3-7 shows MEI state transitions for various operations. Bus operations are described in Table 3-4 on
page 141
.

Table 3-7. MEI State Transitions

(Page 1 of 3)

Operation

Cache

Operation

Bus

Sync

WIM

Current

Cache

State

Next

Cache

State

Cache Actions

Bus Operation

Load (T = 0)

Read

No

x0x

I

Same

Cast out of modified block (as
required).

Write-with-kill

Pass 4-beat read to memory queue.

Read

Load (T = 0)

Read

No

x0x

E,M

Same

Read data from cache.

Load (T = 0)

Read

No

x1x

I

Same

Pass single-beat read to memory
queue.

Read

Load (T = 0)

Read

No

x1x

E

Same

Pass single-beat read to memory
queue.

Read

Load (T = 0)

Read

No

x1x

M

Same

Pass single-beat read to memory
queue.

Read

lwarx

Read

Acts like other reads but bus operation uses special encoding.

Store (T = 0)

Write

No

00x

I

Same

Cast out of modified block (if neces-
sary).

Write-with-kill

Pass RWITM to memory queue.

RWITM

Store (T = 0)

Write

No

00x

E,M

M

Write data to cache.

Store ¦ stwcx.

(T = 0)

Write

No

10x

I

Same

Pass single-beat write to memory
queue.

Write-with-flush

Store ¦ stwcx.

(T = 0)

Write

No

10x

E

Same

Write data to cache.

Pass single-beat write to memory
queue.

Write-with-flush

Store ¦ stwcx.
(T = 0)

Write

No

10x

M

Same

Push block to write queue.

Write-with-kill

Store (T = 0)
or stwcx.

Write

No

x1x

I

Same

Pass single-beat write to memory
queue.

Write-with-flush

Store (T = 0)
or stwcx.

Write

No

x1x

E

Same

Pass single-beat write to memory
queue.

Write-with-flush

Store (T = 0)
or stwcx.

Write

No

x1x

M

Same

Pass single-beat write to memory
queue.

Write-with-flush

Push block to write queue

Write-with-kill

stwcx.

Conditional

write

If the reserved bit is set, this operation is like other writes except the bus operation uses a special
encoding.

dcbf

Data-cache-

block flush

No

xxx

I,E

Same

Pass flush.

Flush

Same

I

State change only.

dcbf

Data-cache-

block flush

No

xxx

M

I

Push block to write queue.

Write-with-kill

Note: Single-beat writes are not snooped in the write queue.

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