Epson ETX-945 - Manual (Page 35)

ETX-945 User Manual 1.02 www.diamondsystems.com Page 35
5.4 BIOS POST Codes
The POST codes used by the ETX-945 ’s on-board BIOS appear in the table below.
Code Function
CFh Test CMOS read/write functionality
C0h Early chipset initialization: Disable shadow RAM, L2 cache (socket 7 and below), program
basic chipset registers
C1h Detect memory: Auto detection of DRAM size, type and ECC, auto detection of L2 cache
(socket 7 and below)
C3h Expand compressed BIOS code to DRAM
C5h Call chipset hook to copy BIOS back to E000 & F000 shadow RAM
01h Expand the Xgroup codes located in physical memory address 000:0
02h Reserved
03h Initial Super I/O_Early Init switch
04h Reserved
05h Blank out screen; Clear CMOS error flag
06h Reserved
07h Clear 8042 interface; Initialize 8042 self test
08h Test special keyboard controller for Winbond 977 series Super I/O chips; enable keyboard
interface
09h Reserved
0Ah Disable PS/2 mouse interface (optional); auto-detect ports for keyboard and mouse
followed by a port and interface swap (optional); reset keyboard for Winbond 977 series
Super I/O chips
0Bh-
0Dh Reserved
0Eh Test F000h segment shadow to see whether it is read/write capable or not. If test fails,
keep beeping the speaker
0Fh Reserved
10h Auto detect flash type to load appropriate flash read/write codes into the run time area in
F000 for ESCD & DMI support
11h Reserved
12h Use “walking 1’s” algorithm to check out interface in CMOS circuitry. Also set real time
clock power status and then check for override
13h Reserved