Grass Valley 8920MUX - Manual (Page 42)

42 8920MUX Instruction Manual
Functional Description
Serial to Parallel Converter and EDH/EDA Error Processor
This circuit converts the serial data stream to the parallel data using the
regenerated clock signal. Deserialized data passes through the EDH pro-
cessor. The EDH processor checks for a possible data or bit error in the
incoming data. Any error is reported to an FPGA internal register.
27Mhz Phase Lock Loop (PLL)
From the incoming 27 MHz clock, the PLL generates an internal, locked 27
MHz signal or produces an approximate 27 MHz free running clock in the
event no input signal is detected.
Field Programmable Gate Array (FPGA)
The FPGA contains 3 independent blocks:
• Ancillary space manager
• 6.144 Mhz clock generator
• CPU interface
The ancillary space manager allows the user to manipulate the embedded
audio groups (G1 through G4). The User can delete or replace an existing
audio group without damaging the SD video stream or other data types in
the ancillary space.
The clock generator, using Direct Digital Synthesis (DDS), generates a 6.144
MHz AES3 carrier clock from the incoming 27 Mhz.
The CPU interface provides connection between the board hardware and
the CPU. From the FPGA, the CPU reads out current board status and
writes back user commands to the hardware.
Multiplexer (MUX)
The MUX chip multiplexes the selected digital audio channels into the
digital video stream. It supports 20- or 24-bit synchronous audio data with
a 48 kHz sample rate. The MUX chip supports the generation and insertion
of EDH information according to SMPTE RP 165.
Parallel to Serial Converter
The 8920MUX uses a standard 10-bit 270 Mbs Serializer.