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Sundance SMT395 User Manual

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Version 1.1.7

Page 3 of 26

SMT395 User Manual

Table of Contents

Revision History ....................................................................................................... 2

Contacting Sundance............................................................................................... 4

Notational Conventions ........................................................................................... 5

C60 ......................................................................................................................... 5

Register Descriptions .............................................................................................. 5

Outline Description .................................................................................................. 6

Block Diagram .......................................................................................................... 7

Architecture Description.......................................................................................... 7

TMS320C6416T ......................................................................................................... 8

Boot Mode............................................................................................................... 9

Flash Boot.......................................................................................................... 9

EMIF Control Registers......................................................................................... 10

SDRAM .................................................................................................................... 11

FLASH ..................................................................................................................... 11

FLASH Paging ................................................................................................. 11

Virtex-II Pro FPGA .................................................................................................. 11

External Clock......................................................................................................... 12

Version control ....................................................................................................... 12

Reprogramming the firmware and boot code ...................................................... 12

FPGA resources ..................................................................................................... 13

Interrupts............................................................................................................... 13

Communication ports ............................................................................................ 13

SDB ...................................................................................................................... 13

SDB Clock selection .......................................................................................... 13

RSL ....................................................................................................................... 13

Global bus............................................................................................................. 13

CONFIG & NMI ..................................................................................................... 13

Timer..................................................................................................................... 14

IIOF interrupt......................................................................................................... 14

LED ....................................................................................................................... 15

TTL ....................................................................................................................... 15