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6 software applications, 1 example0, 2 example1 – Sundance SMT8091 User Manual

Page 14: Software applications, Example0, Example1

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6 Software applications

The SMT8091 comes with a couple of examples.
The examples are designed using

3L Diamond DSP

and show how you can use the

features of the system and how to process the samples acquired by the ADC in the
DSP.
The SMT8091 is also supported by

3L Diamond FPGA

and examples can be provided

on request to place processing in the FPGA.
Please refer to

www.3L.com

for more information about Diamond.

6.1 Example0

The application configures the FPGA of the SMT391-VP and the SMT391 to sample
the incoming signal. The samples are stored in a 16KB FIFO inside the FPGA of the
SMT338-VP. The content of the FIFO is sent to the SMT395-VP for further
processing (FFT) and display.
A GUI running on the host allows to control the settings of the system.

6.2 Example1

The application configures the FPGA of the SMT391-VP and sets up the ADC and
the clock generator of the SMT391. The samples are stored in the on-board DDR
SDRAM of the SMT338-VP before being sent to the SMT395-VP for further
processing ( FFT) and display. Data are stored in files on the host PC.
Note that the maximum sampling frequency allowed when using the DDR SDRAM
memory is 810Msps.
In the example the sampling frequency is fixed to 808Msps and you cannot use the
GUI to change the settings of the SMT391.
Also, in the example, the amount of data stored in the DDR SDRAM is set to
1Msamples per channel.
Note that writing files on the host machine is a relatively slow process and therefore
this example runs slower than the previous one.

External clock: use the external clock when ticked instead of the on-board

clock generator.

ChI -> ChQ: Input I of the ADC is sampled by both channels.
Frequency: configure the sampling frequency of the ADC.
Analog Gain: change the analog gain of the ADC. refer to the ADC user

manual

Offset Compensation: Refer to the ADC user manual
Reset: reset the pipeline of data inside the FPGA of the SMT338-VP
DRDA: refer to the ADC user manual
Built In Test: switch on the test mode of the ADC. refer to the ADC user

manual

User Manual SMT8091

Page 14 of 16

Last Edited: 15/09/2006 11:54:00