Sundance SMT362 - Manual (Page 7)

4.2 Module Description
4.2.1 Mechanical Interface
This module conforms to the TIM standard for single width modules. It requires an additional
3.3V power supply (as present on all Sundance TIM carrier boards) that must be provided by
the two diagonally opposite mounting holes.
4.2.2 Processor
The module incorporates two TMS320C6455 DSPs.
A JTAG interface is provided to enable application debugging via a suitable JTAG controller
and software. The DSPs’ JTAG interfaces are chained and available only on the Top TIM
connector. Typically, the JTAG controller this will be an SMT107 or 310/Q and TI Code
Composer Studio. This is an invaluable interface that enables the application programmer to
quickly debug a ‘chain’ of processors in single or multi-processor situations.
The DSPs have two external memory interfaces. One connects directly to the DDR2 (2
devices of 128M bytes clocked at 250MHz:DDR2-500) and the other (EMIFA, clocked at
133MHz) is used to interface to the remaining peripherals.
Each DSP provides 4 chip selects (numbered 2-5) on its EMIFA interface. The function of
each is shown below;
Chip
select
Base Address
(hex)
DSPA DSPB
CE2 A0000000 FPGA FPGA
CE3 B0000000 Flash Unused
CE4 C0000000 HPI of DSPB Unused
CE5 D0000000 FPGA configuration Unused
Separate to the EMIFA, the DSP provides an interface solely for the connection of DDR2
memory. This is addressed as shown here;
DDR2 E0000000 DDR2 SDRAM DDR2 SDRAM
4.2.3 Flash
A 4Mbyte flash memory is provided with direct access by DSP A. This device contains boot
code for the DSP and the configuration data for the FPGA.
This device is directly connected to DSP A. This is an 8-bit wide device.
The flash is mapped with address bits 0 & 1 (byte addressing) connected to the top address
of the flash so a sector erase will need to erase 4 sectors at once. This is equivalent to
having a flash of 32 128Kwords sectors (instead of 128 32Kwords sectors). The flash is only
accessible byte-wise so it gives a total capacity of the flash of 4MB.
4.2.4 DSP Reset
The DSPs’ configuration is determined during the reset process. The state of the EMIF
address lines is examined, and this determines the on-chip peripheral status.
User Manual SMT362 Page 7 of 30 Last Edited: 29/04/2009 08:56