Sundance SMT338-VP - Manual (Page 14)

Functional description
This section describes in detail the implementation of the board.
Memory banks
Memory is organised in two independent banks.
Both banks can be accessed at the same time.
The following diagram shows how the DDR SDRAM components are organized
within a memory bank:
DDR SDRAM
32 Meg x 16 bits
1
6-bi
ts da
ta bus
DDR SDRAM
32 Meg x 16 bits
1
6-bi
ts da
ta bus
32-
b
its d
a
ta b
u
s
Chip Enable
FPGA
Figure 4: DDR SDRAM components bank organization
One bank is made from two 32M x 16-bits DDR SDRAM components
(
MT46V32M16FN ), each of them having a 16-bit data bus. Memory components are
accessed in pairs.