Sundance SMT130 v.1.0 - Manual (Page 39)

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999
13.3.7 Mailbox Write/Read Interrupt Status Register(Offset: Write 0xD8, BAR0
Read 0xDA, BAR0)
Bits Name Description
15 EN15 1=Mailbox 15 has requested a PCI or Local write/read
interrupt
0=Mailbox 15 has not requested a PCI or Local write/read
interrupt
14 EN14 Same as above for mailbox 14
13 EN13 Same as above for mailbox 13
12 EN12 Same as above for mailbox 12
11 EN11 Same as above for mailbox 11
10 EN10 Same as above for mailbox 10
9 EN9 Same as above for mailbox 9
8 EN8 Same as above for mailbox 8
7 EN7 Same as above for mailbox 7
6 EN6 Same as above for mailbox 6
5 EN5 Same as above for mailbox 5
4 EN4 Same as above for mailbox 4
3 EN3 Same as above for mailbox 3
2 EN2 Same as above for mailbox 2
1 EN1 Same as above for mailbox 1
0 EN0 Same as above for mailbox 0
Register cleared by writing 1, writing 0 has no effect
Table 16 : Mailbox Write/Read Interrupt Status Register
13.3.8 INTREG Register(Offset 0x40, BAR1)
Bits Name Description
15 - Reserved
14 - Reserved
13 - Reserved
12 - Reserved
11 - Reserved