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SMT130 User Manual V1.0
Table of Contents
1
Introduction ..................................................................................................................................... 8
2
Functional Description .................................................................................................................... 9
3
Setting Up the SMT130................................................................................................................. 10
4
Memory Map ................................................................................................................................. 11
4.1
PCI Bridge Chip Internal Register (BAR0) ........................................................................... 11
4.2
I/O Space Register Assignments (BAR1) ............................................................................ 11
4.3
Memory Space Assignments(BAR2).................................................................................... 12
5
DSP Resource Memory Map ........................................................................................................ 13
6
Shared Memory Resource ............................................................................................................ 14
7
Comports....................................................................................................................................... 15
8
Comport to PCI Interface .............................................................................................................. 16
8.1
Comport Registers (Offset 0x10, BAR1) .............................................................................. 16
8.2
Control Register (Offset 0x14, BAR1) .................................................................................. 16
8.3
Status Register (Offset 0x14, BAR1 , Read-Only) ............................................................... 17
8.4
Interrupt Control Register (Offset 0x18, BAR1) ................................................................... 18
9
JTAG Controller ............................................................................................................................ 20
10
Using the SMT130 External/Internal JTAG with TI Tools. ............................................................ 22
11
Firmware Upgrades ...................................................................................................................... 23
12
Global/Local Bus Transfers, DSP <-> PCI................................................................................... 25
12.1
Mailbox Accesses................................................................................................................. 25
12.1.1
Doorbell Interrupts ....................................................................................................... 26
12.2
DSP Interrupt Control ........................................................................................................... 26
12.3
DSP To Local Aperture 0 control and Accessing................................................................. 27
12.3.1
Global bus access protocol ......................................................................................... 29
13
Interrupts ....................................................................................................................................... 32
13.1
SMT130-To-PCI Interrupts ................................................................................................... 32
13.2
PCI-To-SMT130 Interrupts ................................................................................................... 33
13.3
Interrupt Registers................................................................................................................ 33
13.3.1
PCI Interrupt Configuration Register(Offset 0x4C, BAR0) .......................................... 33
13.3.2
PCI Interrupt Status Register(Offset 0x48, BAR0) ...................................................... 35
13.3.3
Local Bus Interrupt Mask Register(Offset 0x77, BAR0).............................................. 36
13.3.4
Local Bus Interrupt Status Register(Offset 0x76, BAR0) ............................................ 37
13.3.5
PCI Mailbox WRITE/READ Interrupt Control Register(Offset: Write 0xD0, BAR0 Read
0xD2, BAR0) ................................................................................................................................. 37
13.3.6
Local Bus Mailbox WRITE/READ Interrupt Control Register(Offset: Write 0xD4, BAR0
Read 0xD6, BAR0) ....................................................................................................................... 38
