2 registers, Page 5, I/o bank 0 i/o port offset: 00 hex – read/write – Sensoray 621 User Manual
Page 7: I/o bank 1 i/o port offset: 04 hex – read/write, I/o bank 2 i/o port offset: 08 hex – read/write, Bank 0 interrupt flags offset: 14 hex – read only, Bank 1 interrupt flags offset: 18 hex – read only, Bits marked with an * are read only, I/o channels 0-31, I/o channels 32-63
Sensoray Model 621/721 Instruction Manual
Page 5
5.2 Registers
I/O bank 0 I/O port
Offset: 00 hex – Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
I/O CHANNELS 0-31
I/O bank 1 I/O port
Offset: 04 hex – Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
I/O CHANNELS 32-63
I/O bank 2 I/O port
Offset: 08 hex – Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X X X X X X X X X X X X X X X X X X X X X X X X
I/O CHANNELS 64-71
Bank 0 edge capture flags
Offset: 0C hex – Read only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CAPTURE FLAGS CHANNELS 0-31
Bank 1 edge capture flags
Offset: 10 hex – Read only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CAPTURE FLAGS CHANNELS 32-63
Bank 0 interrupt flags
Offset: 14 hex – Read only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
INTERRUPT FLAGS CHANNELS 0-31
Bank 1 interrupt flags
Offset: 18 hex – Read only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
INTERRUPT FLAGS CHANNELS 32-63
Bank 0 edge select register
Offset: 1C hex – Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
EDGE SELECT REGISTERS CHANNELS 0-31
Bank 1 edge select register
Offset: 20 hex – Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
EDGE SELECT REGISTERS CHANNELS 32-63
Bank 0 arm capture register
Offset: 24 hex – Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ARM CONTROL REGISTERS CHANNELS 0-31
Bank 1 arm capture register
Offset: 28 hex – Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ARM CONTROL REGISTERS CHANNELS 32-63
Bank 0 interrupt enable register
Offset: 2C hex – Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
INTERRUPT ENABLE REGISTERS CHANNELS 0-31
Bank 1 interrupt enable register
Offset: 30 hex – Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
INTERRUPT ENABLE REGISTERS CHANNELS 32-63
Data direction/Misc./Status register
Offset: 34 hex – Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
GIRQ
*
X
X
X
IRQ3
*
IRQ2
*
IRQ1
*
IRQ0
*
CAP3
*
CAP2
*
CAP1
*
CAP0
*
X
X
LOE
GIE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ARM
X
X
X
X
X
DDR9
68-71
DDR8
64-67
DDR7
56-63
DDR6
48-55
DDR5
40-47
DDR4
32-39
DDR3
24-31
DDR2
16-23
DDR1
8-15
DDR0
0-7
Bits marked with an * are read only.