Sensoray 621 - Manual (Page 6)

Sensoray Model 621/721 Instruction Manual Page 4
2. Installation
The installation of the Model 621/721 into a PCI or Compact PCI system is straight forward as no
special adjustment (jumpers) are required. Follow the directions given in the 621/721 programming
guide.
3. Reset
After a system reset or at power up the 621/721 is in its default state:
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Global interrupt enable (GIE) is disabled
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Channel interrupt enables are disabled
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Event capture enables are indeterminate
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Edge polarity selections are indeterminate
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All I/O channels are all set to input mode
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Output registers are indeterminate
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Channel 64 through 71 are set to simple I/O mode (no latching/output enable)
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Light emitting diode ‘D1’ will be on (controlled by LOE bit, which is set to zero).
4. Device and Vendor Identification
This is the information that identifies a 621/721 board in the PCI system.
Device ID: 9050 Sub Device ID: 6000
Vendor ID: 10B5 Sub Vendor ID: 0001
5. Digital I/O Interface
5.1 Overview
The 621/721 board provides 72 digital I/O (DIO) channels. 64 of the channels have edge detection
capability, and eight channels have Input Latch and 3-state Output Enable capability.
DIO channels 0 to 63 are divided into eight groups of eight channels. Each group may be configured either as
inputs or outputs by programming the associated data direction register (DDR). These 64 channels have the
ability to detect and capture edge transition events. Each channel may be independently to capture either positive
or negative edges. A captured event may optionally generate an interrupt.
DIO channels 64 to 71 are divided into two groups of four channels. Each group can be configured
either as inputs or outputs by programming its associated data direction register (DDR). In addition to
the standard DIO mode, a Latch/Output Enable (LOE) mode is available for channels 64 to 71. Setting
the latch enable register (LOE) enables this mode, which applies to all eight channels. The LOE mode
enables the DIO input signals (on channels 64 to 71) to be latched by asserting the LATCH signal; the
latched data may be read at any time. In addition, the outputs in this mode are tri-stated unless the user
asserts the OUTEN input line.