Measurement Computing CIO-DI48 - Manual (Page 13)

5.0 DATA REGISTERS
5.1 INTRODUCTION
Each CIO-DI## is composed of parallel input chips. Each inp ut buffer senses eight
input pins. The ports are arranged in sets o f three, with an intervening register that is
not used. This scheme allows compatibility with software written to control 82C55
based boards when the 82C55 is used as all inputs. (On those boards, every fourth
register is a control register.)
The first address, or BASE ADDRESS +0, is determined by setting a bank of switches
on the board.
To read data from an input register, a byte is read representing the status of up to eight
digital input lines.
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