BECKHOFF FC7501 - Manual (Page 13)

Configuration
FC750x 13
Check Timing
If selected, then in each cycle the exact real-time behaviour of access to the card is monitored. If not maintained
(actual values are read too early, or set values are written too late) then a corresponding counter located in the
process data is incremented. This monitoring has only a very small impact on the performance, so that there is no
disadvantage to using it in normal applications. In applications with very short cycle times and where performance
margins are very tight, however, it can be switched off.
Watchdog
The SERCON816 Sercos ASIC used has a hardware watchdog that monitors regular PC access, activating phase
0 if the accesses cease. The number of cycles that the watchdog will tolerate is given here. The watchdog is deac-
tivated if the figure supplied is 0.
NC Access Time
A figure is given here for the time required by the NC in each cycle for reading the actual values and writing the set
values. This value is only used by the internal time slot calculation, so that possible time slot problems can be
seen in advance (cf. Check Timing Errors).
NC Shift Time
The NC shift time can be used to delay the time at which the NC begins to read the actual values. The value gives
the number of µs after the last AT. The default value of 50µs ensures in normal cases that even if there is a small
amount of jitter in the real-time system, the ATs, and therefore the actual values, have safely arrived at the master
before the NC takes action. If more than one Sercos ring is in use, it may be necessary to adjust this value, since
the NC accesses all the rings at more or less the same time, but the connected devices in particular rings mean
that the last ATs arrive at different times. Since the Sercos rings on the bus are synchronised in hardware, the
following rule applies: The NC shift time should be set on the various rings in such a way that the resulting tNcAc-
cess time (see timing) is about the same on all the rings. In addition to this, the NC shift time should not be much
less than about 20 µs on any ring.
Cycle-Time(3-4)
The cycle time of the highest priority associated task is indicated here. This is used in phases 3 and 4.
Cycle-Time(0-2)
The cycle time in phases 0 to 2 is given here. This is used for the bus start-up.
The following values make it possible to influence the internal time slot calculation, to make modifications of a few
µs in the event of communication problems or loading difficulties. However, this should not be done without the
appropriate Sercos expertise, so that the effects can be estimated.
JT1 User
The value set here alters the jitter JT1 used in the internal time slot calculation.
JT2 User
The value set here alters the jitter JT2 used in the internal time slot calculation.
JTSCyc User
The value set here alters the jitter JTSCyc used in the internal time slot calculation.
T3 User
The value set here alters the time T3 used in the internal time slot calculation.
T4 User
The value set here alters the time T4 used in the internal time slot calculation.