3 phy connection, 1 required ethernet phy signals, Phy connection – BECKHOFF PHY User Manual
Page 6: Required ethernet phy signals

PHY Connection
Slave Controller
– Application Note PHY Selection Guide
3
3
PHY Connection
Figure 2 shows the principle connection between ESC
5
and PHY. The clock source of Ethernet PHYs and ESC
has to be the same quartz or quartz oscillator. TX_CLK is usually not connected unless automatic TX Shift
compensation is used, because the ESCs do not incorporate a TX FIFO. The TX signals can be delayed inside
the ESC for TX_CLK phase shift compensation. LINK_STATUS is an LED output indicating a 100 Mbit/s (Full
Duplex) link.
Refer to ESC data sheet Section III for details about Ethernet PHY connection of a specific ESC.
Ethernet PHY
2
5
M
H
z
OSC_OUT
OSC_IN
CLK25OUT
RX_DV
RXD[3:0]
RX_ER
TX_EN*
TXD[3:0]*
RX_CLK
RX_DV
RXD[3:0]
RX_ER
TX_EN
TXD[3:0]
RX_CLK
TX_CLK
CLK25
CRS
TX_ER
COL
LINK_MII
LINK_STATUS
25 MHz
Option: one quartz oscillator for
ESC and PHYs
MDIO
MDC*
MDIO
MDC
4
K
7
V
CC I/O
* Configuration input (ESC dependent)
TX signal delay
configuration
0 ns
10 ns
20 ns
30 ns
TX_CLK
IP Core opt. with
Auto-TX-Shift:
ESC
Figure 2: PHY Connection
5
ESC10/20 uses TX_CLK of a PHY as the clock source of the ESC. FPGAs with IP Core only support the quartz oscillator
alternative.
3.1
Required Ethernet PHY signals
Table 1: Required Ethernet PHY signals using MII
Signal
Required
Comment
CLK25
Mandatory
Shared 25 MHzclock source between ESC and PHY
LINK_STATUS
Mandatory
LINK LED signal, required for fast link loss reaction time
RX_CLK
Mandatory
RX_DV
Mandatory
RXD[3:0]
Mandatory
RX_ER
Mandatory
Required for error detection and error source localization
COL
Not used
EtherCAT uses full duplex only
CRS
Not used
EtherCAT uses full duplex only
TX_CLK
Optional
Optional for automatic TX Shift compensation
TXD[3:0]
Mandatory
TX_ER
Not used
Connect to GND
MDIO
Optional
Recommended especially for debugging
MDC
Optional
Recommended especially for debugging
Table 2: Required Ethernet PHY signals using RMII
Signal
Required
Comment
REF_CLK
Mandatory
Shared 50 MHz clock source between ESC and PHY
LINK_STATUS
Mandatory
LINK LED signal, required for fast link loss reaction time
CRS_DV
Mandatory
RXD[1:0]
Mandatory
RX_ER
Mandatory
Required for error detection and error source localization
TX_EN
Mandatory
TXD[1:0]
Mandatory
MDIO
Optional
Recommended especially for debugging
MDC
Optional
Recommended especially for debugging