BECKHOFF PHY - Manual (Page 10)

EtherCAT over Optical Links (FX)
Slave Controller – Application Note PHY Selection Guide 7
4.4 Examples of Ethernet PHYs assumed to be incompatible with EtherCAT requirements
The following Ethernet PHYs are currently assumed or known to be incompatible with EtherCAT – because
they do not support MDI/MDIX-auto-crossover which became state-of-the-art for many recent PHYs:
 AMD Am79C874, Am79C875 (datasheet: no MDI/MDIX-auto-crossover)
 Broadcom BCM5208R (datasheet: no MDI/MDIX-auto-crossover)
BCM5214 (datasheet: only RMII/SMII interface)
 Cortina Systems LXT970A, LXT971A, LXT972A, LXT972M, LXT974, LXT975 (datasheet:
no MDI/MDIX-auto-crossover)
 Davicom Semiconductor DM9761 (datasheet: no MDI/MDIX-auto-crossover)
 Marvell 88E3016 (datasheet: only RGMII interface)
 Micrel KSZ8041 Rev. A3 (hardware test: no preamble maintenance) and maybe
previous revisions
 SMSC/Microchip LAN83C185 (datasheet: no MDI/MDIX-auto-crossover)
 STMicroelectronics STE100P (datasheet: no MDI/MDIX-auto-crossover)
 Teridian 78Q2120C (datasheet: no MDI/MDIX-auto-crossover)
 VIA Technology VT6103F, VT6303L (datasheet: no MDI/MDIX-auto-crossover)
5 EtherCAT over Optical Links (FX)
The intention of this chapter is to share current knowledge about FX operation with EtherCAT. The solutions
and comments are still work-in-progress, they are possibly subject to change or even incomplete. Most of the
presented example schematics have not been implemented in hardware, but they are expected to be working.
5.1 ESCs with native FX support
ESCs with FX support have individual PHY reset outputs for each port. This PHY reset output is intended to
hold the PHY and the transceiver in reset state while the ESC is in reset state, and additionally, to issue a reset
cycle when a link failure is detected by the enhanced link detection mechanism.
If at least one port is configured for FX operation, all ports have to use the individual PHY reset outputs. This is
especially important for enhanced link detection, since all the PHY reset outputs are used for link down
signalling instead of auto-negotiation restart, which is not used anymore
– regardless of the port using FX or TX.
Ethernet PHY
Port 0
nPHY_RESET_OUT(0) nRESET
ESC Transceiver Port 0
MDC/MDIO MDC/MDIO
V CC
Vcc
nReset
Ethernet PHY
Port 1
nRESET
Transceiver Port 1
MDC/MDIO
V CC
Vcc
nReset
nPHY_RESET_OUT(1)
Figure 3: PHY reset connection for ESCs with FX support or mixed FX/TX support
5.2 ESCs without native FX support
5.2.1 Standard Link Detection
The Enhanced link detection restarts auto-negotiation between the PHYs if a certain level of receive errors is
reached. With FX PHYs, auto-negotiation is not available (it is a 100Base-TX feature). Typically, PHYs ignore
the restart auto-negotiation request. As a consequence, the EtherCAT slave controller waits endlessly for the
link to go down. Other PHYs might get into a dead-lock, because auto-negotiation is enabled by the restart auto-
negotiation request, but it will not complete due to the FX operation mode.
Thus, Enhanced Link Detection has to be turned off for FX links (unless Enhanced FX Link Detection is used,
which is recommended. See later for more information). It is strongly recommended to use PHYs which are
supporting Far-end-Fault (FEF) completely if Enhanced link detection is not used (refer to Section I of the ESC
data sheets for more information on FEF).