Sample output – Artesyn MVME2500 VxWorks 6.8 User Guide (April 2014) User Manual
Page 32
Sample Output
MVME2500 VxWorks 6.8 User Guide (6806800L66C)
32
Core: E500, Version: 5.1, (0x80211051)
Clock Configuration:
CPU0:1000 MHz, CPU1:1000 MHz,
CCB:400 MHz,
DDR:400 MHz (800 MT/s data rate) (Asynchronous), LBC:25 MHz
L1: D-cache 32 kB enabled
I-cache 32 kB enabled
Board: MVME2500
Emerson Network Power, Embedded Computing
Monitor Version: 1.5
FPGA Seq.Ver: 2.5
Is not VME system controller
I2C: ready
SPI: ready
DRAM: Initializing.... DDR: 2 GiB (DDR3, 64-bit, CL=6, ECC on)
L2: 512 KB enabled
MMC: FSL_ESDHC: 0
EEPROM: Read MAC Address
PCIE2 connected as Root Complex (base addr ffe09000)
PCIE2 on bus 00 - 00
PCIE3 connected as Root Complex (base addr ffe08000)
PCIE3 on bus 01 - 01
PCIE1 connected as Root Complex (base addr ffe0a000)
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