Avalue ESM-QM57 - Manual (Page 27)

User ’s Manual
ESM- QM57 User ’s Manual 27
2.4.2.4 Flat Panel LVDS Signals
Signal Signal Description
BIASON Controls panel contrast voltage.
DIGON Controls panel digital power.
ENBKL# Controls backlight power enable.
I
2
C_DAT, I
2
C_CLK
I
2
C interface for panel parameter EEPROM. This EERPOM is mounted on the
LVDS receiver. The data in the EEPROM allows the EXT module to automatically
set the proper timing parameters for a specific LCD panel.
2.4.2.5 LPC Signals
Signal Signal Description
LPC_FRAME# LPC frame indicates the start of an LPC cycle
LPC_AD[0:3] LPC multiplexed address, command and data bus
LPC_DRQ[0:1]# LPC serial DMA request
LPC_CLK LPC clock output - 33MHz nominal
LPC_SERIRQ LPC serial interrupt
2.4.2.6 Miscellaneous Signals
Signal Signal Description
I
2
C_CK General purpose I
2
C port clock output
I
2
C_DAT General purpose I
2
C port data I/O line
SPKR Output for audio enunciator - the "speaker" in PC-AT systems
BIOS_DISABLE#
Module BIOS disable input. Pull low to disable module BIOS. Used to allow
off-module BIOS implementations.
KB_RST#
Input to module from (optional) external keyboard controller that can force a reset.
Pulled high on the module. This is a legacy artifact of the PC-AT.
KB_A20GATE
Input to module from (optional) external keyboard controller that can be used to
control the CPU A20 gate line. The A20GATE restricts the memory access to the
bottom megabyte and is a legacy artifact of the PC-AT. Pulled low on the module.
2.4.2.7 PCI Express Signals
Signal Signal Description
PCIE_TX[0:4] +/- PCI Express Differential Transmit Pair 0-4
PCIE_RX[0:4] +/- PCI Express Differential Receive Pair 0-4
PCIE0_CK_REF+/-
Reference clock output for PCI Express lanes 0-7 and for PCI Express Graphics
lanes 0-15