ADLINK DAQe-2502 - Manual (Page 43)

Operation Theory 33
Data Format in FIFO and Mapping
With hardware-based waveform generation, D/A conversions are
updated automatically by CPLD rather than application software.
Unlike the conventional software-based waveform generation, the
precise hardware timing control guarantees non-distorted wave-
form generation even when host CPU is under heavy loading.
Detailed function setup are discussed later on this chapter.
NOTE When using waveform generation mode, all the four
DACs in the same D/A group must be configured for the
same mode. However, any one of the DAC can be dis-
abled. If you need to use the software update mode, you
can use another D/A group on the DAQ-/DAQe-/PXI-
2502 card.
Setting up the DACs
Before using the DACs, you must setup the reference source and
its polarity. Each DAC has its own reference and polarity settings.
For example, the internal voltage reference of D/A Group A is tied
to internal +10V. However, you can still connect external reference
through AOEXTREF (pin 5 on CN2) to a +3.3V voltage source,
giving each DAC in D/A Group A two reference options: 10V or
3.3V. However, DA update timing, trigger source, and trigger/stop
mode are all the same throughout a D/A Group.
The DAQ-/DAQe-/PXI-2502/2501 card provides the capability to
fine tune the voltage reference from the external source. The
external reference is fed thru an onboard calibrated circuit, with
programmable offset. You can use this capability to generate pre-
cise D/A outputs.
CAUTION The range of external voltage reference should be within
±10V.