Maxim Integrated Fremont (MAXREFDES6) ZedBoard - Manual (Page 5)

Fremont (MAXREFDES6#) ZedBoard Quick Start Guide
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3. Included Files
The top level of the hardware design is a Xilinx PlanAhead Project (.PRR) for Xilinx
PlanAhead version 14.2. The Verilog-based arm_system_stub.v module provides
FPGA/board net connectivity, and instantiates the wrapper that carries both the Zynq®
Processing System and AXI_MAX11100 custom IP core that interface to the Pmod port.
This is supplied as a Xilinx software development kit (SDK) project that includes a
demonstration software application to evaluate the Fremont subsystem reference
design. The lower level c-code driver routines are portable to the user’s own software
project.
Processor
ARM
(Zynq)
AXI MAX11100
Custom IP Core
DDR
Pmod
Connector
JA1
JTAG
USB
Programmer
Programming
Options
Quad-SPI Flash
SD Card
Internal
BRAM
Zynq EPP
Figure 3. Block Diagram of FPGA Hardware Design