Make Noise MATHS Classic - Manual (Page 8)

MATHS is FUN
FLIP-FLOP (1-Bit Memory)
In this patch CH. 1 Trigger IN acts as the “Set” input, and CH. 1 BOTH Contrl IN acts as the “Reset”
input. Apply Reset signal to CH. 1 BOTH Control IN. Apply Gate or logic signal to CH. 1 Trigger IN. Set
Rise to Full CCW, Fall to Full CW, Vari-Response to Linear. Take “Q” output from EOC. Patch EOC to
CH. 4 Signal to achieve “NOT Q” at the EOC OUT. This patch has a memory limit of about 3 minutes,
after which it forgets the one thing you told it to remember.
Voltage Controlled Pulse Delay Processor
Apply Trigger or Gate to Trigger IN if CH. 1. Take output from End Of Rise. RISE parameter will set the
delay and Fall parameter will adjust width of the resulting delayed pulse.
Voltage Controlled Clock Divider
Clock signal applied to Trigger IN CH. 1 or 4 is processed by a divisor as set by Rise parameter.
Increasing Rise sets divisor higher, resulting in larger divisions. Fall time will adjust the width of the
resulting clock. If the Width is adjusted to be greater the the total time of the division the output will
remain “high.” Take output from EOR or EOC.
Logic Invertor
Apply logic gate to CH. 4 Signal IN. Take output from CH. 4 EOC.
Half Wave Rectification
Apply bi-polar signal to CH. 1, 2, 3, 4 IN. Take output from OR out. Mind the normalizations to the OR
buss.
Full Wave Rectification
Mult signal to be rectified to both CH. 2 and 3 IN. CH 2 Scaling/ Inversion set to Full CW, CH. 3
Scaling/ Inversion set to Full CCW. Take output from OR Out. Vary the Scaling.
ADD, Subtract Control Signals
Apply signals to be added/ subtracted to any combination of Signal IN CH. 1,2,3,4 (when using CH.
1,4 Rise and Fall must be set to full CCW, and Cycle switch not engaged). Set Scale/ Inversion panel
controls for channels to be added, to full CW. Set Scale/ Inversion panel controls for channels to be
subtracted to full CCW. Take output from SUM OUT.
Peak Detector
Patch signal to be detected to CH. 1 Signal IN. Set Rise and Fall to 3 'o' Clock. Take output from
Signal OUT. Gate out from EOR OUT.
Voltage Mirror
Apply Control Signal to be mirrored to CH. 2 Signal IN. Set CH. 2 Scale/ Inversion panel control to Full
CCW. With nothing inserted at CH. 3 Signal IN (so as to generate an offset), set CH. 3 Scale/
Inversion panel control to full CW. Take output from SUM OUT. This patch will also work as a Logic
Invertor.
Multiplication
Apply positive going Control Signal to be multiplied to CH1 or 4 Signal IN. Set Rise to full CW, Fall to
Full CCW. Apply positive going, multiplier Control Signal to BOTH Control IN. Take output from
corresponding Signal OUT.