Cirrus Logic EDB9307A - Manual (Page 13)

EDB9307A
Technical Reference Manual
DS667DB1
©
Copyright 2006 Cirrus Logic, Inc. 13
Page 9
The two connectors provide a daughter card interface for making custom circuits. J4 is the Memory
Expansion connector and J5 is the Peripheral Expansion connector.
The entire memory bus is connected to J5. It is recommended that the bus signals be buffered if adding
additional memory. However if a CPLD or FPGA is attached there is no reason to buffer. Use proper
engineering practices when using the high-speed memory bus with daughter cards.
The Peripheral Expansion bus has the signals for features not implemented on the EDB9307A board and
for commonly used signals.
Page 10
Two video interfaces are provided. The main video interface is VGA. An LCD interface is also provided
however there is no LCD screen included with the development kit. The LCD interface is pin compatible
with previous Cirrus Logic ARM9 development boards. A 4-wire touch screen interface is also included
and is pin compatible with previous Cirrus Logic ARM9 development boards.
Page 11
An external USB 2.0 High-speed Peripheral device is provided. The USB device allows a Host to see the
board as a Mass Storage device. The USB interface chip is connected to the lower 16-bits of the
memory bus.
Page 12
Audio is supported by a Cirrus Logic CS4271 device. Two-channel audio out and line-level audio in is
supported. The audio device communicates to the EP9307 through the I
2
S interface and audio clocks
are generated by the EP9307. The audio in is line level, it is not a microphone-level input. Like the serial
EEPROM, the CS4271 is controlled by the SPI frame signal and EGPIO6. EGPIO6 must be low in order
to communicate to the CS4271 device. As mentioned before, only one SPI
™ device can be enabled at a
time.