Cirrus Logic AN331 - Manual (Page 2)

AN331
2
2. Implementation Requirements for the CS5381
The block diagram shown in Figure 1 shows an implementation of the CS5381 A/D. Notice that the same analog
signal is applied to each of the A/D converters within the CS5381. The required mathematical operation is then per-
formed in either a Digital Signal Processor (DSP) or Field Programmable Gate Array (FPGA).
It is very important to note that the addition (or subtraction) must be performed with synchronously sampled and time
aligned data pairs. Within the serial audio interface, the Left followed by Right channel data pairs are synchronously
sampled data. However, the Right followed by Left channel data pairs are shifted in time by one sample period rel-
ative to each other and the addition or subtraction of these pairs will produce erroneous results. Please refer to the
Cirrus Logic application note AN282 “The 2-Channel Audio Interface: A Tutorial” for more information concerning
the serial audio interface and synchronously sampled data pairs.
Figure 1. Mono-Mode Block Diagram
CS5381
Right Channel A/D
CS5381
Left Channel A/D
Data
Processing in
DSP or FPGA
Analog Input
Serial Audio Interface
Mono-Channel
Output