Cirrus Logic CS4385A - Manual (Page 3)

DS837F2 3
CS4385A
7.1.2 Chip Revision [Read Only] .................................................................................................... 37
7.2 Mode Control 1 (Address 02h) ....................................................................................................... 37
7.2.1 Control Port Enable (CPEN) .................................................................................................. 37
7.2.2 Freeze Controls (FREEZE) ................................................................................................... 37
7.2.3 PCM/DSD Selection (DSD/PCM) .......................................................................................... 38
7.2.4 DAC Pair Disable (DACx_DIS) .............................................................................................. 38
7.2.5 Power Down (PDN) ............................................................................................................... 38
7.3 PCM Control (Address 03h) ........................................................................................................... 38
7.3.1 Digital Interface Format (DIF) ................................................................................................ 38
7.3.2 Functional Mode (FM) ........................................................................................................... 39
7.4 DSD Control (Address 04h) ............................................................................................................ 39
7.4.1 DSD Mode Digital Interface Format (DSD_DIF) .................................................................... 39
7.4.2 Direct DSD Conversion (DIR_DSD) ...................................................................................... 40
7.4.3 Static DSD Detect (STATIC_DSD) ........................................................................................ 40
7.4.4 Invalid DSD Detect (INVALID_DSD) ..................................................................................... 40
7.4.5 DSD Phase Modulation Mode Select (DSD_PM_MODE) ..................................................... 40
7.4.6 DSD Phase Modulation Mode Enable (DSD_PM_EN) ......................................................... 40
7.5 Filter Control (Address 05h) ........................................................................................................... 41
7.5.1 Interpolation Filter Select (FILT_SEL) ................................................................................... 41
7.6 Invert Control (Address 06h) .......................................................................................................... 41
7.6.1 Invert Signal Polarity (Inv_xx) ................................................................................................ 41
7.7 Group Control (Address 07h) ......................................................................................................... 41
7.7.1 Mutec Pin Control (MUTEC) .................................................................................................. 41
7.7.2 Channel A Volume = Channel B Volume (Px_A=B) .............................................................. 42
7.7.3 Single Volume Control (SNGLVOL) ...................................................................................... 42
7.8 Ramp and Mute (Address 08h) ...................................................................................................... 42
7.8.1 Soft Ramp and Zero Cross Control (SZC) ............................................................................ 42
7.8.2 Soft Volume Ramp-Up After Error (RMP_UP) ...................................................................... 43
7.8.3 Soft Ramp-Down Before Filter Mode Change (RMP_DN) .................................................... 43
7.8.4 PCM Auto-Mute (PAMUTE) .................................................................................................. 43
7.8.5 DSD Auto-Mute (DAMUTE) ................................................................................................... 43
7.8.6 Mute Polarity and Detect (MUTEP1:0) .................................................................................. 44
7.9 Mute Control (Address 09h) ........................................................................................................... 44
7.9.1 Mute (MUTE_xx) ................................................................................................................... 44
7.10 Mixing Control (Address 0Ah, 0Dh, 10h, 13h) .............................................................................. 45
7.10.1 De-Emphasis Control (PX_DEM1:0) ................................................................................... 45
7.10.2 ATAPI Channel Mixing and Muting (ATAPI) ........................................................................ 46
7.11 Volume Control (Address 0Bh, 0Ch, 0Eh, 0Fh, 11h, 12h, 14h, 15h) ............................................ 47
7.11.1 Digital Volume Control (xx_VOL7:0) ................................................................................... 47
7.12 PCM Clock Mode (Address 16h) .................................................................................................. 47
7.12.1 Master Clock Divide by 2 Enable (MCLKDIV) ..................................................................... 47
8. FILTER PLOTS ..................................................................................................................................... 48
9. PARAMETER DEFINITIONS ................................................................................................................ 52
10. PACKAGE DIMENSIONS ................................................................................................................. 53
11. ORDERING INFORMATION .............................................................................................................. 53
12. REFERENCES .................................................................................................................................... 54
13. REVISION HISTORY ......................................................................................................................... 55