Cirrus Logic CDB4384 - Manual (Page 3)

DS620DB1 3
CDB4384
CDB4384 SYSTEM OVERVIEW
The CDB4384 evaluation board is an excellent means of quickly evaluating the CS4384. The CS8416 digital audio
interface receiver provides an easy interface to digital audio signal sources including the majority of digital audio
test equipment. The evaluation board also allows the user to supply external PCM or DSD clocks and data through
PCB headers for system development.
The CDB4384 uses the CDB4385 as a base PCB board. For this reason, there may be additional circuitry on board
which is not populated as it has no function for this device.
The CDB4384 schematic has been partitioned into 9 schematics shown in Figures 2 through 10. Each partitioned
schematic is represented in the system diagram shown in Figure 1. Notice that the system diagram also includes
the interconnections between the partitioned schematics.
1. CS4384 DIGITAL TO ANALOG CONVERTER
A description of the CS4384 is included in the CS4384 datasheet.
2. CS8416 DIGITAL AUDIO RECEIVER
The system receives and decodes the standard S/PDIF data format using a CS8416 digital audio receiver (Figure
6). The outputs of the CS8416 include a serial bit clock, serial data, left-right clock, and a 128/256 Fs master clock.
The CS8416 data format is fixed to I
²
S. The operation of the CS8416 and a discussion of the digital audio interface
is included in the CS8416 datasheet.
The evaluation board has been designed such that the input can be either optical or coaxial, see Figure 6. However,
both inputs cannot be driven simultaneously.
Switch position 7 of S1 sets the output MCLK-to-LRCK ratio of the CS8416. This switch should be set to 256 (closed)
for inputs Fs
≤ 96 kHz and 128 (open) for Fs ≥ 64 kHz. The CS8416 must be manually reset using ‘HW RST’ (S2)
or through the software when this switch is changed.
3. INPUT FOR CLOCKS AND DATA
The evaluation board has been designed to allow interfacing to external systems via headers J11 and J7. Header
J11 allows the evaluation board to accept externally generated PCM clocks and data. The schematic for the
clock/data input is shown in Figure 7. Switch position 6 of S1 selects the source as either CS8416 (open) or header
J11 (closed).
Header J7 allows the evaluation board to accept externally generated DSD data and clocks. The schematic for the
clock/data input is shown in Figure 8. A synchronous MCLK must still be provided via Header J11. Switch position
8 of S1 selects either PCM (open) or DSD (closed).
Please see the CS4384 datasheet for more information.
4. INPUT FOR CONTROL DATA
The evaluation board can be run in either a stand-alone mode or with a PC. Stand-alone mode uses the CS4384 in
hardware mode and the mode pins are configured using switch positions 1 through 5 of S1. PC mode uses software
to setup the CS4384 through I
²
C using the PC’s serial port. PC mode is automatically selected when the serial port
(RS232 or USB) is attached and the CDB4384 software is running. The latest control software may be downloaded
from: www.cirrus.com/msasoftware.
Header J15 offers the option for external input of RST and SPI
™
/I
²
C clocks and data. The board is setup from the
factory to use the on-board microcontroller in conjunction with the supplied software. To use an external control