Cirrus Logic AN165 - Manual (Page 2)

AN165
2 AN165REV1
4. PCB LAYOUT CHECKLIST
• Connect analog and digital ground together
with a 1/16 inch trace under the CS4297A. A
direct connection between analog and digital
ground will reduce the differential-mode radia-
tion and improve the EOS (Electrical Over-
stress) capabilities of the CS4297A.
• Construct a "clean" chassis ground on the PCB
around the I/O connectors, and connect the I/O
ground to the system frame ground.
• Connect chassis ground to digital ground in a
quiet area, away from the CS4297A.
• The ferrite bead and decoupling capacitor com-
bination shown in the block diagram on page
one of this document, form a low-pass filter to
remove the common-mode voltages. The de-
coupling capacitor must be terminated to a
clean (free of digital noise) I/O chassis ground.
A separate analog ground return path between
the I/O connectors and analog ground plane
must be maintained to reduce loop areas.
• Chassis and analog planes should be identical
on all layers, and the gap or "moat" between
planes should be 1/8 inch to prevent coupling
between planes. The absolute minimum moat
spacing is 1/16 inch. Do not overlap digital and
analog ground planes.
• Never route digital traces or digital planes un-
der the analog or I/O chassis ground areas. An-
alog components should be located over analog
planes and digital components should be locat-
ed over digital planes.
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/
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