Cirrus Logic AN Integrating CobraNet into Audio Products - Manual (Page 14)

FAQ P RELIMINARY
12
CS18101 (CM-2) AppNote1 - rev 1.1 Jan, 2004
w w w . c i r r u s . c o m
FAQ
The following are some frequently asked questions about the CM-2.
Q: Does the CM-2 make the CM-1 obsolete?
A: No! The CM-2 does not offer the number of audio channels that the CM-1 does. For
this reason (and others) the CM-1 will remain in production.
Q: Can a host system be made to use either the CM-1 or the CM-2?
A: Yes. The electrical interfaces are almost identical, and with a little software design
effort either can be made to work. This way a designer can develop a "low-channel-
count" version of a design that uses the CM-2 and a "high-channel-count" version
that uses the CM-1.
Q: What benefits are there to using the CM-2 module rather than embedding the CM-2
circuit on my own board?
A: If the CM-2 module is used then it can be an optional add-on to your “box”. It also
allows you to use the CM-1 or possibly future CobraNet Modules without major
redesign.
Additionally, you can customize the circuit to better match your target price point and
feature set. For example, by removing the redundant Ethernet connector or replacing
the switching DC/DC converter with a cheaper linear regulator, the cost and size of
your system is reduced.
Q: If I embed the CM-2 circuit into my PCB design, what board qualities should I expect
to need?
A: The CM-2 module is a 6-layer board with 6-mil traces and spaces. This is what we
recommend people use if embedding the CM-2 circuit into their design. The CM-2
module also has some small components on the back side of the PCB, which we also
recommend. If the redundant Ethernet connector will be omitted, it might be possible
to put all components on the top side of the PCB and use a 4-layer board. However,
we have not tried this ourselves.
Q: Why does the CM-2 (and the CM-1) use a 24.576MHz master audio clock rather than
a more typical 12.288MHz clock?
A: 12.288MHz clocks are not as well suited for some phase-locked loops (PLLs).
Specifically, the PLLs in Xilinx FPGAs cannot operate with a 12.288MHz clock. Also,
other PLLs which may work do operate better with the higher clock.