Asus A7VL133-VM - Manual (Page 59)

ASUS A7VL133-VM User’s Manual 59
4. BIOS SETUP
4. BIOS SETUP
Byte Merge [Disabled]
To optimize the data transfer on PCI, this merges a sequence of individual
memory writes (bytes or words) into a single 32-bit block of data. However,
byte merging may only be done when the bytes within a data phase are in a
prefetchable address range. Configuration options: [Disabled] [Enabled]
DRAM Read Latch Delay [Auto]
Configuration options: [-0.01 ns] [0.75 ns] [1.72 ns] [2.69 ns] [-0.01 ns]
[2.11 ns] [3.08 ns] [4.05 ns]...[Auto]
Memory Early/Delay Write [Auto]
Configuration options: [0.0 ns] [0.5 ns] [1.0 ns] [1.5 ns] [-0.5 ns]
[-1.0 ns] [-1.5 ns] [Auto]
DIMM Interleave Setting [Auto]
Configuration options: [Auto] [Disabled]
Graphics Aperture Size [64MB]
This feature allows you to select the size of mapped memory for AGP graphic
data. Configuration options: [4MB] [8MB] [16MB] [32MB] [64MB]
[128MB] [256MB]
VGA Shared Memory Size [16MB]
Configuration options: [8MB] [16MB] [32MB]
Video Memory Cache Mode [UC]
USWC (uncacheable, speculative write combining) is a new cache technol-
ogy for the video memory of the processor. It can greatly improve the dis-
play speed by caching the display data. You must set this to UC (uncacheable)
if your display card cannot support this feature; otherwise your system may
not boot. Configuration options: [UC] [USWC]