HP StorageWorks 2.128 SAN Director Switch - Manual (Page 157)

Fabric OS 5.x administrator guide 157
Testing components to and from the HBA
1. Connect to the switch and log in as admin.
2. Issue the
fPortTest
command.
See the HP StorageWorks Fabric OS 5.x command reference guide for information on the command
options. The following example executes the
fPortTest
command 100 times on port 8 with payload
pattern
0xaa55
, pattern width 2 (meaning word width) and a default payload size of 512 bytes:
Table 27 provides a list of additional tests that can be used to determine the switch components that are
not functioning properly. See the HP StorageWorks Fabric OS 5.x command reference guide for additional
command information.
Correcting link failures
A link failure occurs when a server or storage device is connected to a switch, but the link between the
server or storage device and the switch does not come up. This prevents the server or storage device from
communicating through the switch.
If the
switchShow
command or LEDs indicate that the link has not come up properly, use one or more of
the following procedures.
Determining whether the negotiation was successfully completed
The port negotiates the link speed with the opposite side. The negotiation usually completes in 1–2
seconds; however, sometimes the speed negotiation fails.
NOTE: Skip this procedure if the port speed is set to a static speed through the
portCfgSpeed
command.
switchname:admin> fporttest 100,8,0xaa55,2, 512
Will use pattern: aa55 aa55 aa55 aa55 aa55 aa55 ...
Running fPortTest ........
port 8 test passed.
value = 0
Table 27 Switch component tests
Test Function
portloopbacktest
Functional test of port N to N path.
portregtest
Read and write test of the ASIC SRAMs and registers.
spinsilk
Functional test of internal and external transmit and receive paths at full speed.
sramretentiontest
Test to verify that the data written into the miscellaneous SRAMs in the ASIC are
retained after a 10-second wait.
crossporttest
Test to verify that the functional components of the switch.
turboramtest
Test to verify that the on chip SRAM located in the 2 Gbit/sec ASIC is using the
Turbo-Ram BIST circuitry. These same SRAMs are tested by
portregtest
and
sramretentiontest
using PCI operations, but for this test the BIST controller is
able to perform the SRAM write and read operations at a much faster rate.
statstest
Test to verify that the ASIC statistics counter logic.
Related Switch Test Option:
itemlist
Option to restrict the items to be tested to a smaller set of parameter values that
you pass to the switch.