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1 family 10h amd phenom™ processor features – AMD Phenom 10h User Manual

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PID:44109 Rev:3.00 - November 2007

Family 10h AMD Phenom™ Processor Product Data Sheet

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Family 10h AMD Phenom™ Processor Features

1 Family 10h AMD Phenom™ Processor Features

The following is a list of features and capabilities of the Family 10h AMD Phenom™ processor.

• Compatible with Existing 32-Bit Code Base

• Including support for SSE, SSE2, SSE3, SSE4a, ABM, MMX™, 3DNow!™ technology and legacy x86

instructions

• Runs existing operating systems and drivers
• Local APIC on the chip

• AMD64 Technology

• AMD64 technology instruction set extensions
• 64-bit integer registers, 48-bit virtual addresses, 40-bit physical addresses
• Sixteen 64-bit integer registers
• Sixteen 128-bit SSE/SSE2/SSE3 registers

Multi-Core Architecture

• Triple-core or quad-core options
• AMD Balanced Smart Cache

• Discrete L1 and L2 cache structures for each core
• Shared L3 cache structure

Machine Check Architecture

• Includes hardware scrubbing of major ECC protected arrays

Cache Structures

64-Kbyte 2-Way Associative ECC-Protected L1 Data Cache

• Two 64-bit operations per cycle, 3-cycle latency

64-Kbyte 2-Way Associative Parity-Protected L1 Instruction Cache

• With advanced branch prediction

• 512-Kbyte 16-Way Associative ECC-Protected L2 Cache

• Exclusive cache architecture storage in addition to L1 caches

• 2048-Kbyte (2-Mbyte) Maximum 32-way Associative ECC-Protected L3 Cache

• Shared cache architecture storage in addition to exclusive L1 and L2 caches

• Floating-Point Unit

• AMD Wide Floating-Point Accelerator

• 128 bit Floating-Point Unit (FPU)

• Virtualization Features

• SVM disable and lock
• Nested paging
• Rapid Virtualization Indexing

Power Management

• Multiple low-power states
• Independent Dynamic Core Technology
• AMD CoolCore™ Technology
• Dual Dynamic Power Management
• System Management Mode (SMM)
• ACPI-compliant, including support for processor performance states
• Supported power states: C0, C1, C1E, S0, S1, S3, S4, S5

Electrical Interfaces

• DDR2 SDRAM: SSTL_1.8 per JEDEC specification
• DDR2 SDRAM-like electrical specifications also used for clock, reset and test signals

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