Chapter 3, Chipset overclocking configuration – Elitegroup H61H2-M19 (V1.0) User Manual
Page 70
Chapter 3
H61H2-M19 USER MANUAL
66
CAS# Latency(tCL) (7)
This item determines the operation of DDR SDRAM memory CAS (column address
strobe). It is recommended that you leave this item at the default value. The 2T
setting requires faster memory that specifically supports this mode.
Row Precharge Time(tRP) (7)
This item specifies Row precharge to Active or Auto-Refresh of the same bank.
RAS# to CAS# Delay(tRCD) (7)
This item specifies RAS# to CAS# delay to Rd/Wr command to the same bank.
RAS# Active Time(tRAS) (20)
This item specifies the RAS# active time.
Write Recovery Time(tWR) (8)
This item specifies the write recovery time.
Row Refresh Cycle Time(tRFC) (59)
This item specifies the row refresh cycle time.
Write to Read Delay(tWTR) (4)
This item specifies the write to read delay time.
Active to Active Delay(tRRD) (4)
This item controls the active bank x to active bank y in memory clock cycles.
Read CAS# Precharge(tRTP) (4)
This item controls the Read to precharge delay for memory devices, in memory clock
cycles.
Performance Memory Profiles (Automatic)
This item allows you to select the memory mode: Automatic, Manual, XMP Profile 1
or 2.
Press
Four Active Window Delay(tFAW) (16)
This item controls the four bank activate time in memory clock cycles.
Chipset OverClocking Configuration
Scroll to this item and press
Aptio Setup Utility - Copyright (C) 2012 American Megatrends, Inc.
Version 2.15.1229. Copyright (C) 2012 American Megatrends, Inc.
Main
Advanced
Chipset
M.I.B III
Boot Security Exit
F1:General Help
+/- : Change Opt.
Enter : Select
:Select Screen
:Select Item
F2:Previous Values
F3:Optimized Defaults
F4:Save & Exit
ESC:Exit
The selection of Performance Memory
Profiles which impacts memory
sizing behavior.
Memory Multiplier Configuration
Performance Memory Profiles
[Automatic]
Memory Timing Configuration
CAS# Latency(tCL)
7
RAS# to CAS# Delay(tRCD)
7
Row Precharge Time(tRP)
7
RAS# Active Time(tRAS)
20
Write Recovery Time(tWR)
8
Row Refresh Cycle Time(tRFC)
59
Active to Active Delay(tRRD)
4
Write to Read Delay(tWTR)
4
Read CAS# Precharge(tRTP)
4
Four Active Window Delay(tFAW)
16